초록 ▼

A circuit and method for demodulating a pp

A circuit and method for demodulating a pp

대표청구항 ▼

A digital demodulating circuit for use in a time-division multiple access channel, having a radio frequency processing circuit for filtering a p4-differentially quadrature phase shift keying (DQPSK) modulated signal, converting the filtered signal to base band I channel and a Q channel signal compon

A digital demodulating circuit for use in a time-division multiple access channel, having a radio frequency processing circuit for filtering a p4-differentially quadrature phase shift keying (DQPSK) modulated signal, converting the filtered signal to base band I channel and a Q channel signal components, said digital demodulating circuit comprising: first and second low-pass filters for low-pass filtering said I channel and Q channel signal components, respectively; first and second analog/digital converters for oversampling respective filtered analog signals output from said first and second low-pass filters to generate respective I and Q channel data, wherein said I and Q channel data include a plurality of data sets; an intermediate buffer memory for temporarily storing said I and Q channel data; a clock generator for providing a clock for use in oversampling of said first and second analog/digital converters and for controlling write speed of said intermediate buffer memory; a reference waveform memory for storing data representative of a reference training modulation signal; a time synchronizer for calculating complex correlation function values between I and O channel data for each of said plurality of data sets stored in said intermediate buffer memory and said data representative of a reference training modulation signal stored in said reference waveform memory, detecting a maximum peak value within a time slot of the calculated complex correlation function values, and generating a signal indicative of a selected one of said data sets of the I and Q channel data stored in said intermediate buffer memory, said selected data set corresponding to said maximum peak value; a phase determining circuit for determining the phase of the signal generated by said time synchronizer every predetermined time period; a differential phase detecting and binary data determining circuit for detecting a phase difference according to the phase determined from said phase determining circuit and determining binary data adapted for a p-differentially quadrature phase shift keying (DQPSK) modulation characteristic according to the detected phase difference; and a parallel/serial converter for converting binary data output from said differential phase detecting and data determining circuit into serial data to generate a differential phase value by the unit of 2 bits.