초록 ▼

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnect

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD. MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

대표청구항 ▼

A computer system, comprising: a plurality of processor-memory elements (PME\s), each processor-memory element (PME) containing a processor, a memory, and a multi-bit parallel data path therebetween; a plurality of nodes interconnected as a multi-dimensional network cluster, each node containing a p

A computer system, comprising: a plurality of processor-memory elements (PME\s), each processor-memory element (PME) containing a processor, a memory, and a multi-bit parallel data path therebetween; a plurality of nodes interconnected as a multi-dimensional network cluster, each node containing a plurality of processor-memory elements (PME\s); and a cluster controller for said plurality of nodes; wherein each processor-memory element (PME) of a node has a plurality of communication paths to processor-memory elements (PME\s) within the node and at least one communication path to a processor-memory element (PME) external to the node.