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Vector processor adopting a memory skewing scheme for preventing degradation of access performance 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/16
출원번호 US-0275388 (1994-07-15)
우선권정보 JP-0175115 (1993-07-15)
발명자 / 주소
  • Sakakibara Tadayuki (Kunitachi JPX) Tanaka Teruo (Hachioji JPX) Tamaki Yoshiko (Kodaira JPX) Kitai Katsuyoshi (Palo Alto CA) Inagami Yasuhiro (Kodaira JPX)
출원인 / 주소
  • Hitachi, Ltd. (Tokyo JPX 03)
인용정보 피인용 횟수 : 54  인용 특허 : 0

초록 ▼

A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the addr

대표청구항 ▼

A vector processor, comprising: a storage unit including a number (N) of memory modules, which number is given by a power of two and in which an interleave method of successively assigning continuous addresses to memory modules which differ from one to another is adopted; a number (N) of access requ

이 특허를 인용한 특허 (54)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
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  10. Hatakeyama, Izumi, Address generator, interleave unit, deinterleaver unit, and transmission unit.
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  11. Chauvel,Gerard, Address space priority arbitration.
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  12. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
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  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
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  17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
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  18. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
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  19. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
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  20. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
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  21. Jakovljevic, Radomir; Beric, Aleksandar; Van Dalen, Edwin; Milicev, Dragan, Electronic apparatus having parallel memory banks.
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  22. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
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  23. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
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  24. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  25. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  26. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
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  27. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  28. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  29. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  30. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  31. Jakovljevic, Radomir; Beric, Aleksandar; Van Dalen, Edwin; Milicev, Dragan, Intelligent parametric scratchap memory architecture.
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  32. Reid, Alastair David, Interleaving data accesses issued in response to vector access instructions.
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  33. Reid, Alastair David, Interleaving data accesses issued in response to vector access instructions.
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  34. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  35. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  36. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  37. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
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  38. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
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  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  41. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  42. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  43. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  44. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  45. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  46. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  47. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
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  48. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
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  49. Greger, Michael J.; Wehage, Eric R.; Sakuta, Toshiyuki, Remote configuration access for integrated circuit devices.
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  50. James, David V.; Rajamanickam, Jagadeesan; Wanzakhade, Sanjay M.; Stephens, Jr., Michael C., Search engine device and method for generating output search responses from multiple input search responses.
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  51. Master,Paul L.; Watson,John, Storage and delivery of device features.
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  52. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
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  53. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
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  54. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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