초록 ▼

A multi-level interconnect structure and method. A first plurality of interconnect lines (14) is located on an insulator layer (12) of semiconductor body (10). A first layer of low dielectric constant material (20), such as an organic polymer, fills an area between the first plurality of interconnec

A multi-level interconnect structure and method. A first plurality of interconnect lines (14) is located on an insulator layer (12) of semiconductor body (10). A first layer of low dielectric constant material (20), such as an organic polymer, fills an area between the first plurality of interconnect lines (14a-c). The first layer of low dielectric constant material (20) has a height not greater than a height of the first plurality of interconnect lines (14). A first layer of silicon dioxide (18) covers the first layer of low dielectric constant material (20) and the first plurality of interconnect lines (14).

대표청구항 ▼

A method for forming an interconnect structure on a semiconductor body, comprising the steps of: a. forming a plurality of spaced interconnect lines on said semiconductor body; b. filling the space between all adjacent interconnect lines, having a distance therebetween no greater than a given distan

A method for forming an interconnect structure on a semiconductor body, comprising the steps of: a. forming a plurality of spaced interconnect lines on said semiconductor body; b. filling the space between all adjacent interconnect lines, having a distance therebetween no greater than a given distance, with an insulating material having a dielectric constant lower than the dielectric constant of silicon dioxide and greater than or equal to one, and leaving a sidewall spacer in at least partially open field area between adjacent interconnect lines, having a distance therebetween greater than said given distance; and c. depositing a first layer of silicon dioxide over said interconnect lines, said open field area and said insulating material.