초록 ▼

An enhanced peak detector circuit for the amplitude demodulation of an incoming amplitude modulated signal is provided. In its simplest form, the enhanced peak detector circuit includes a forward biased NPN transistor, a peak detecting segment coupled to the base-emitter junction of the transistor;

An enhanced peak detector circuit for the amplitude demodulation of an incoming amplitude modulated signal is provided. In its simplest form, the enhanced peak detector circuit includes a forward biased NPN transistor, a peak detecting segment coupled to the base-emitter junction of the transistor; and a peak holding capacitor leading from the collector of the transistor and connected in parallel to the peak detecting segment. The peak detecting segment includes a parallel connected peak detecting capacitor and a resistor. When the base-emitter junction of the transistor is conducting, both the peak detecting capacitor and the peak holding capacitor are charging. Conversely, when the base-emitter junction of the transistor is back biased, the peak detecting capacitor discharges through the resistor and the collector remains open such that the peak holding capacitor remains charged.

대표청구항 ▼

A peak detector circuit for amplitude demodulation of an incoming signal, the peak detector circuit comprises: a rectifying means; a peak detecting segment coupled to the rectifying means; and a peak holding capacitor switchably connected via the rectifying means to be in a parallel relationship wit

A peak detector circuit for amplitude demodulation of an incoming signal, the peak detector circuit comprises: a rectifying means; a peak detecting segment coupled to the rectifying means; and a peak holding capacitor switchably connected via the rectifying means to be in a parallel relationship with the peak detecting segment; wherein an output signal appears across the peak holding capacitor that represents the peaks of the incoming signal.