초록 ▼

A system is disclosed for synthesizing field programmable gate array (FPGA) implementations from high level circuit descriptions. A designer may describe circuits using a textual language or a graphics tool. The system will compile such circuit descriptions into technology mapped descriptions for us

A system is disclosed for synthesizing field programmable gate array (FPGA) implementations from high level circuit descriptions. A designer may describe circuits using a textual language or a graphics tool. The system will compile such circuit descriptions into technology mapped descriptions for use with FPGA\s. The system will support both random logic circuits and data path circuits. The system uses advanced optimization techniques to produce efficient FPGA implementations. Thus, the system produces high quality results while providing users with a high level of abstraction in design, and thus frees the user from architectural details of the target FPGA.

대표청구항 ▼

A structured circuit synthesis system for optimizing a circuit implementation in a field programmable gate array, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the system comprising: a computer processor; means for sto

A structured circuit synthesis system for optimizing a circuit implementation in a field programmable gate array, wherein said field programmable gate array comprises a plurality of programmable logic cells connected by programmable routing, the system comprising: a computer processor; means for storing a description of a first electronic circuit design module specifying an output signal and a polarity of said output signal, and a second electronic circuit design module specifying an input signal and a polarity of said input signal, said output signal of the first module corresponding to the input signal of said second module; and means for receiving the input signal and the output signal and reversing the signal polarities of said input signal and said output signal to synthesize multiple modules simultaneously to reduce the number of programmable logic cells required to implement said first module and said second module in the field programmable gate array.