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Integrated circuit memory having high speed and low power by selectively coupling compensation components to a pulse gen

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
  • H03K-005/06
출원번호 US-0573306 (1995-12-15)
발명자 / 주소
  • Rothenberger Roland D. (Poway CA) Sullivan Greg T. (Escondido CA) Tung Kenny Y. (Escondido CA)
출원인 / 주소
  • Unisys Corporation (Blue Bell PA 02)
인용정보 피인용 횟수 : 63  인용 특허 : 4

초록

A memory in an integrated circuit chip includes an array of memory cells and a read/write circuit which performs precharge and sense operations on the array for a time interval that is set by the width of a pulse signal. This pulse signal is generated by a pulse generator circuit which contains tran

대표청구항

A memory, in an integrated circuit chip, which is comprised of: an array of memory cells, coupled to a read/write circuit which performs a predetermined operation on said array for a time interval that is set by the width of a pulse signal; a pulse generator, coupled to said read/write circuit, whic

이 특허에 인용된 특허 (4)

  1. You Jei-Hwan (Suwon KRX), Data retention mode control circuit.
  2. Yamauchi Naoki (Itami JPX) Kobayashi Hiroshi (Itami JPX), Delay circuit.
  3. Segawa Hiroshi (Itami JPX) Matsumura Tetsuya (Itami JPX), Pulse generating circuit in a semiconductor integrated circuit and a delay circuit therefor.
  4. Houston Theodore W. (Richardson TX), Pulse generator circuit and method.

이 특허를 인용한 특허 (63)

  1. McCollum John L., Antifuse programmed PROM cell.
  2. Patrick J. Mullarkey, Apparatus for adjusting delay of a clock signal relative to a data signal.
  3. Hanriat Stephane,FRX ; Schoellkopf Jean-Pierre,FRX, Circuit for validating simulation models.
  4. Keeth Brent, Clock vernier adjustment.
  5. Keeth Brent, Clock vernier adjustment.
  6. Patrick J. Mullarkey, Computer system having memory device with adjustable data clocking.
  7. Mullarkey, Patrick J., Computer system having memory device with adjustable data clocking using pass gates.
  8. Manning Troy A., Delay-locked loop with binary-coupled capacitor.
  9. Manning Troy A., Delay-locked loop with binary-coupled capacitor.
  10. Manning Troy A., Delay-locked loop with binary-coupled capacitor.
  11. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
  12. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
  13. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
  14. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
  15. Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
  16. Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
  17. Lee,Terry R.; Jeddeloh,Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
  18. Beal Samuel W. ; Kaptonoglu Sinan ; Lien Jung-Cheun ; Shu William ; Chan King W. ; Plants William C., Enhanced field programmable gate array.
  19. John E. McGowan, Field programmable gate array with mask programmed input and output buffers.
  20. McGowan John E., Field programmable gate array with mask programmed input and output buffers.
  21. Chan, Yuen H.; Chen, Ann H.; Pelella, Antonio R.; Wang, Shie ei, High performance pseudo dynamic pulse controllable multiplexer.
  22. Keeth, Brent, Memory system with dynamic timing correction.
  23. Baker Russel Jacob ; Manning Troy A., Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory dev.
  24. Baker Russel Jacob ; Manning Troy A., Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same.
  25. Keeth Brent, Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same.
  26. Mullarkey Patrick J., Method and apparatus for adjusting data timing by delaying clock signal.
  27. Keeth, Brent; Manning, Troy A., Method and apparatus for adjusting the timing of signals over fine and coarse ranges.
  28. Brent Keeth ; Terry R. Lee ; Kevin Ryan ; Troy A. Manning, Method and apparatus for bit-to-bit timing correction of a high speed memory bus.
  29. Keeth, Brent; Lee, Terry R.; Ryan, Kevin; Manning, Troy A., Method and apparatus for bit-to-bit timing correction of a high speed memory bus.
  30. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  31. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  32. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  33. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  34. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  35. Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.
  36. Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.
  37. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
  38. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
  39. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
  40. Harrison,Ronnie M., Method and apparatus for generating a sequence of clock signals.
  41. Manning Troy A., Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal.
  42. Troy A. Manning, Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal.
  43. Manning, Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
  44. Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
  45. Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
  46. Troy A. Manning, Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
  47. Troy A. Manning, Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
  48. Brent Keeth, Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same.
  49. Manning Troy A., Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device.
  50. Troy A. Manning, Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same.
  51. Johnson, Brian; Harrison, Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.
  52. Johnson,Brian; Harrison,Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.
  53. Manning, Troy A., Method for generating expect data from a captured bit pattern, and memory device using same.
  54. Rothenberger Roland D. ; Sullivan Greg T. ; Tung Kenny Yifeng, Precision delay circuit.
  55. Gunyan,Daniel B.; Scott,Jonathan B., Pulse generator.
  56. Fagan, John L.; Bossard, Mark, Selectable delay pulse generator.
  57. Harrison Ronnie M. ; Keeth Brent, Synchronous clock generator including a compound delay-locked loop.
  58. Harrison Ronnie M., Synchronous clock generator including a delay-locked loop signal loss detector.
  59. Harrison Ronnie M. ; Keeth Brent, Synchronous clock generator including delay-locked loop.
  60. Mullarkey Patrick J., Synchronous memory device having an adjustable data clocking circuit.
  61. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
  62. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
  63. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
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