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A process for fabricating a thin film transistor, which comprises crystallizing an amorphous silicon film, forming thereon a gate insulating film and a gate electrode, implanting impurities in a self-aligned manner, adhering a coating containing a catalyst element which accelerates the crystallizati

A process for fabricating a thin film transistor, which comprises crystallizing an amorphous silicon film, forming thereon a gate insulating film and a gate electrode, implanting impurities in a self-aligned manner, adhering a coating containing a catalyst element which accelerates the crystallization of the silicon film, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities. Otherwise, the catalyst element can be incorporated into the structure by introducing it into the impurity region by means of ion implantation and the like. Also a process for fabricating a thin film transistor, which comprises forming a gate electrode, a gate insulating film, and an amorphous silicon film on a substrate, implanting impurities into the amorphous silicon film to form source and drain regions as the impurity regions, introducing a catalyst element into the impurity region by adhering a coating containing the catalyst element of by means of ion doping and the like, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities.

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A method of manufacturing an insulated gate field effect transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating layer on said gate electrode; forming a semiconductor layer over said gate electrode, said gate electrode insulated from said semiconductor

A method of manufacturing an insulated gate field effect transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating layer on said gate electrode; forming a semiconductor layer over said gate electrode, said gate electrode insulated from said semiconductor layer by said gate insulating layer interposed therebetween; forming a mask over said semiconductor layer, wherein said mask is formed in a self-alignment manner with respect to said gate electrode; introducing metal ions into a first region of said semiconductor layer in a self-alignment manner with respect to said mask; introducing impurity ions into a second region of said semiconductor layer in a self-alignment manner with respect to said mask to form source and drain regions.