초록 ▼

A programmable logic array device in which programmable logic regions are arranged in groups of four is provided. The device includes direct connect conductors for carrying signals totally within one group of four regions as well as to certain adjacent programmable logic regions, local conductors fo

A programmable logic array device in which programmable logic regions are arranged in groups of four is provided. The device includes direct connect conductors for carrying signals totally within one group of four regions as well as to certain adjacent programmable logic regions, local conductors for carrying signals within groups and among adjacent groups, and global conductors for carrying device-wide signals. Connections among the various conductors, and between conductors and programmable logic regions, are provided to optimize the connection resources by avoiding switched conductor paths wherever possible.

대표청구항 ▼

A programmable logic array device having first and second substantially orthogonal array dimensions and comprising: a plurality of regions of programmable logic arranged in rows and columns substantially along said first and second orthogonal array dimensions, each of said regions having a plurality

A programmable logic array device having first and second substantially orthogonal array dimensions and comprising: a plurality of regions of programmable logic arranged in rows and columns substantially along said first and second orthogonal array dimensions, each of said regions having a plurality of terminals comprising a plurality of inputs and at least one output, and producing an output signal on said output which is a programmable function of an input signal applied to said inputs of said region, said regions being grouped into logic subsets, each of said logic subsets comprising a plurality of said regions, each of said regions belonging to only one of said logic subsets; a first group of conductors for conducting signals to, from and among said logic subsets, each conductor in said first group of conductors extending along substantially the entire length of one of said first and second orthogonal array dimensions; a second group of conductors, each of said subsets having at least one conductor of said second group of conductors associated therewith, for conducting signals to, from and among said regions in said logic subset; a third group of conductors, each of which conveys signals directly from one of said regions in one of said logic subsets to another of said regions in said one of said logic subsets; a first group of connectors for programmably selectively connecting any conductor in one of said first, second and third groups of conductors to at least one of (a) an input to, and (b) an output of, one of said regions, at least one connector in said first group of connectors connecting at least one conductor in said first group of conductors directly to an input of one of said regions; and a second group of connectors for programmably selectively connecting conductors in said first group of conductors to other conductors in said first and second groups of conductors.