초록 ▼

In multiplex serial data communication circuit network and method, a clock information is always output from a single transmission control apparatus having an oscillation source onto a single signal transmission line. Any one of the other transmission control apparatuses carries out a serial data tr

In multiplex serial data communication circuit network and method, a clock information is always output from a single transmission control apparatus having an oscillation source onto a single signal transmission line. Any one of the other transmission control apparatuses carries out a serial data transmission with the clock pulse signal superposed on the data to be transmitted via the single transmission line. In addition, any one of the transmission control apparatuses extracts the clock information from the clock information superposed data signals on the single transmission line and takes an operation timing within all transmission control apparatuses from the extracted clock pulse signal. Furthermore, a remote DC motor control system and method using the multiplex serial data communication circuit network described above are exemplified. Master station and slave stations in the DC motor control system can be integrated into each plurality of ICs.

대표청구항 ▼

A multiplex serial data communication circuit network comprising: a) a clock pulse oscillation circuit for generating a clock pulse signal; b) a single signal transmission line on which a signal is transmitted bidirectionally in a multiplex time division mode; c) a clock pulse signal output circuit

A multiplex serial data communication circuit network comprising: a) a clock pulse oscillation circuit for generating a clock pulse signal; b) a single signal transmission line on which a signal is transmitted bidirectionally in a multiplex time division mode; c) a clock pulse signal output circuit for transmitting the clock pulse signal generated by the clock pulse oscillation circuit on said single signal transmission line; d) a transmission data generation/output circuit for superposing a transmission data on the clock pulse signal output from said clock pulse signal output circuit; e) a clock pulse signal extraction circuit for receiving signals present on the transmission line and for extracting the clock pules signal from the received signals; and f) means for separating and extracting a signal required to operate therein from among the received signals and for executing a signal processing in synchronization with the extracted clock pules signal.