Ranganathan N. (Tampa FL) Mehrotra Rajiv (Lexington KY)
출원인 / 주소
The University of South Florida (Tampa FL 02)
인용정보
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초록▼
Circuit architecture for dynamic scene analysis uses a difference picture based technique wherein pixel values corresponding to the same position from previous and current frames are inputted to the system during each clock cycle. The difference picture is input to a connected component labeling alg
Circuit architecture for dynamic scene analysis uses a difference picture based technique wherein pixel values corresponding to the same position from previous and current frames are inputted to the system during each clock cycle. The difference picture is input to a connected component labeling algorithm in order to obtain the various connected components in the difference picture. A Sobel edge detector is applied to previous and current frame pixel values, and the resulting data stored in a buffer so that for each pixel, the connected component label of the difference picture, the Sobel edge value in the current frame, and the Sobel edge value in the previous frame are stored. The buffer supplies the data to a series of motion detection processors which are arranged in a systolic array. An alternative arrangement is to arrange the motion detection processors in parallel in a pipeline fashion with no feedback logic. In any case, each processor analyzes a different region of the difference picture in order to detect and classify the type of motion occurring in that region. The difference picture generator, Sobel operators, connected components hardware and buffer, and motion detection processors can be implemented into a CMOS VLSI chip to obtain high speed and real time response.
대표청구항▼
Circuit architecture for dynamic scene analysis, comprising: difference picture generator hardware which takes as inputs pixel values corresponding to the same location in the scene from previous and current time frames and provides as output a representation of the difference picture of the scene,
Circuit architecture for dynamic scene analysis, comprising: difference picture generator hardware which takes as inputs pixel values corresponding to the same location in the scene from previous and current time frames and provides as output a representation of the difference picture of the scene, connected components hardware which takes as input the output of the difference picture generator and provides as output connected component labels of the difference picture, edge detector hardware which take as input pixel values corresponding to the same location in the scene from previous and current time frames and provide as outputs the edge values of the current and previous frames, and a plurality of motion detection processors which analyze separate regions of the difference picture, each of said motion detection processors having hardware which takes as input a connected component label of the difference picture in one region of the difference picture, the edge value in the current frame and the edge value in the previous frame, determines the motion relationship between each pixel and a predetermined set of neighborhood pixels, and provides as output a value representing the type of motion occurring in that region depending upon the motion relationship between each pixel and the neighborhood pixels; wherein each of said motion detection processors has a feature extractor stage which determines the motion parameters of the region; wherein said feature extractor has means for comparing each pixel in the region with the predetermined set of neighborhood pixels to determine the adjacency of the pixel to the neighborhood pixels; wherein said feature extractor has means for determining the number of current frame edge fragments, the number of previous frame edge fragments, a boolean value representing the closedness of the current frame edge fragment, a boolean value representing the closedness of the previous frame edge fragment, and the number of current and previous frame edge points depending on the adjacency of the pixel to the neighborhood pixels; wherein said means for determining the number of current frame edge fragments, the number of previous frame edge fragments, a boolean value representing the closedness of the current frame edge fragment, a boolean value representing the closedness of the previous frame edge fragment, and the number of current and previous frame edge points includes counter means and flip-flop means; wherein said plurality of motion detectors are arranged in a systolic array; and wherein each of said motion detection processors has a labeled picture generator in circuit communication with said feature extractor, said labeled picture generator associating with each pixel a k-bit label, and wherein said feature extractor comprises: (a) a line delay having a plurality of k-bit registers connected in circuit communication, at least one of said k-bit registers corresponding to a predetermined pixel location and at least two other of said k-bit registers corresponding to a predetermined neighbor pixel location of said predetermined pixel location, said predetermined pixel location having associated therewith a predetermined pixel and each of said predetermined neighbor pixel locations having associated therewith a predetermined neighborhood pixel; (b) a plurality of adjacency logic units, each of said adjacency logic units being in circuit communication with: (i) the at least one k-bit register of said line delay corresponding to said predetermined pixel location and (ii) at least one other k-bit register of said line delay, said other k-bit register corresponding to one of said predetermined neighbor pixel locations; and (c) feature extraction logic in circuit communication with said plurality of adjacency logic units.
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