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Programmable logic module and architecture for field programmable gate array device

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0522945 (1995-09-01)
발명자 / 주소
  • El Ayat Khaled A. (Cupertino CA) Bakker Gregory W. (Sunnyvale CA) Lien Jung-Cheun (San Jose CA) Plants William C. (Santa Clara CA) Kaptanoglu Sinan (San Carlos CA) Gopisetty Runip (Los Gatos CA) Chan
출원인 / 주소
  • Actel Corporation (Sunnyvale CA 02)
인용정보 피인용 횟수 : 31  인용 특허 : 0

초록

A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plural

대표청구항

A programmable logic module comprising: a first multiplexer having a plurality of data inputs connected to data input conductors, at least one control input connected to a first control input conductor, and an output connected to a first output conductor; a data flip-flop having a data input, a cloc

이 특허를 인용한 특허 (31)

  1. Liu, Tong; Feng, Sheng; Lien, Jung-Cheun, Field programmable gate array freeway architecture.
  2. Lien, Jung-Cheun; Feng, Sheng; Liu, Tong, Field-programmable gate array architecture.
  3. Liu,Tong; Lien,Jung Cheun; Feng,Sheng; Huang,Eddy C.; Sun,Chung Yuan; Liao,Naihui; Xiong,Weidong, Freeway routing system for a gate array.
  4. Feng, Sheng; Liu, Tong; Lien, Jung-Cheun, Inter-tile buffer system for a field programmable gate array.
  5. Feng,Sheng; Liu,Tong; Lien,Jung Cheun, Inter-tile buffer system for a field programmable gate array.
  6. Feng,Sheng; Liu,Tong; Lien,Jung Cheun, Inter-tile buffer system for a field programmable gate array.
  7. Feng, Sheng; Liu, Tong; Lien, Jung-Cheun, Intra-tile buffer system for a field programmable gate array.
  8. Wilson Stanley ; Chan King W. ; Frappier Mark, Logic function module for field programmable array.
  9. Galbraith Douglas C. ; El Gamal Abbas ; Greene Jonathan W., Logic module with configurable combinational and sequential blocks.
  10. Sun, Chung, Method and apparatus for cascade programming a chain of cores in an embedded environment.
  11. Sun, Chung; Huang, Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.
  12. Sun,Chung; Huang,Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.
  13. Sun,Chung; Huang,Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.
  14. David R. Hembree ; Warren M. Farnworth ; Salman Akram ; Alan G. Wood ; C. Patrick Doherty ; Andrew J. Krivy, Probe card and test system for semiconductor wafers.
  15. Hembree David R. ; Farnworth Warren M. ; Akram Salman ; Wood Alan G. ; Doherty C. Patrick ; Krivy Andrew J., Probe card and testing method for semiconductor wafers.
  16. Hembree,David R.; Farnworth,Warren M.; Akram,Salman; Wood,Alan G.; Doherty,C. Patrick; Krivy,Andrew J., Probe card for semiconductor wafers having mounting plate and socket.
  17. Chua Hua-Thye, Programmable application specific integrated circuit employing antifuses and methods therefor.
  18. Gamal Abbas El ; El-Avat Khaled A. ; Mohsen Amr, Programmable interconnect architecture.
  19. Rupp Charle R., Reconfigurable computer architecture for use in signal processing applications.
  20. Feng, Sheng; Lien, Jung-Cheun; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui, Routing structures for a tileable field-programmable gate array architecture.
  21. Feng, Sheng; Lien, Jung-Cheun; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui; Xiong, Weidong, Tileable field-programmable gate array architecture.
  22. Feng, Sheng; Lien, Jung-Cheun; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui; Xiong, Weidong, Tileable field-programmable gate array architecture.
  23. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.
  24. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.
  25. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.
  26. Jung-Cheun Lien ; Sheng Feng ; Eddy C. Huang ; Chung-Yuan Sun ; Tong Liu ; Naihui Liao TW, Tileable field-programmable gate array architecture.
  27. Lien, Jung-Cheun; Feng, Sheng; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui, Tileable field-programmable gate array architecture.
  28. Lien, Jung-Cheun; Feng, Sheng; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui, Tileable field-programmable gate array architecture.
  29. Lien,Jung Cheun; Sun,Chung Yuan; Liu,Tong; Zhang,Zili; Feng,Sheng; Huang,Eddy C.; Liao,Naihui, Tileable field-programmable gate array architecture.
  30. Liu, Tong; Lien, Jung-Cheun; Feng, Sheng; Huang, Eddy C.; Sun, Chung-Yuan; Liao, Naihui, Tileable field-programmable gate array architecture.
  31. Bryant, Ian; Sun, Chung-Yuan; Feng, Sheng; Lien, Jung-Cheun; Chan, Stephen, User available body scan chain.
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