이 특허를 인용한 특허 (80)

1. Martin, Chris G., Active termination circuit and method for controlling the impedance of external integrated circuit terminals.

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2. Martin, Chris G., Active termination circuit and method for controlling the impedance of external integrated circuit terminals.

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3. Martin,Chris G., Active termination circuit and method for controlling the impedance of external integrated circuit terminals.

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4. Martin,Chris G., Active termination circuit and method for controlling the impedance of external integrated circuit terminals.

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5. Martin,Chris G., Active termination circuit and method for controlling the impedance of external integrated circuit terminals.

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6. Mauthe,Manfred; Icking,Henrik, Adjusting driver stage output impedance.

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7. Jung, Hyun-Key, Apparatus and method for automatic control of current electrodes for electrical resistivity survey.

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8. Jeong, Chun-Seok, Calibration circuit and semiconductor memory device with the same.

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9. Best,Scott C.; Wong,Anthony Koon; Leung,David, Calibration methods and circuits for optimized on-die termination.

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10. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits for optimized on-die termination.

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11. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.

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12. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.

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13. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.

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14. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.

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15. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.

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16. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.

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17. Noda, Shinichi; Ishihara, Hideaki; Suzuki, Akira, Clamp circuit.

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18. Jung, Hae Kang, Data output circuit of semiconductor apparatus.

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19. Male Barry ; Martin William, Digital-to-analog converter employing binary-weighted transistor array.

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20. Nguyen, Huy M.; Gadde, Vijay; Doraiswamy, Sivakumar, Driver calibration methods and circuits.

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21. Nguyen, Huy M.; Gadde, Vijay; Doraiswamy, Sivakumar, Driver calibration methods and circuits.

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22. Nguyen, Huy M.; Gadde, Vijay; Doriaswamy, Sivakumar, Driver calibration methods and circuits.

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23. Nguyen,Huy M.; Gadde,Vijay; Doraiswamy,Sivakumar, Driver calibration methods and circuits.

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24. Pelley, Perry H., Driver with selectable output impedance.

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25. Hsu Pochang ; Nagaraj Ravi, Dual mode input/output interface circuit.

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26. Bhattacharya, Dipankar; Kothandaraman, Makeshwar; Kriz, John C.; Marques, Antonio M.; Morris, Bernard L., Enhanced output impedance compensation.

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27. Goetting F. Erich ; Frake Scott O. ; Kondapalli Venu M. ; Young Steven P., FPGA with a plurality of I/O voltage levels.

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28. Goetting F. Erich ; Frake Scott O. ; Kondapalli Venu M. ; Young Steven P., FPGA with a plurality of I/O voltage levels.

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29. F. Erich Goetting ; Scott O. Frake ; Venu M. Kondapalli ; Steven P. Young, FPGA with a plurality of input reference voltage levels.

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30. Goetting F. Erich ; Frake Scott O. ; Kondapalli Venu M. ; Young Steven P., FPGA with a plurality of input reference voltage levels.

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31. Goetting F. Erich ; Frake Scott O. ; Kondapalli Venu M. ; Young Steven P., FPGA with a plurality of input reference voltage levels grouped into sets.

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32. Edwin S. Law ; Kiran B. Buch ; Glenn A. Baxter ; Raymond C. Pang, Hardwire logic device emulating any of two or more FPGAs.

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33. McClintock, Cameron; Cliff, Richard G.; Wang, Bonnie I., I/O cell configuration for multiple I/O standards.

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34. McClintock,Cameron; Cliff,Richard G.; Wang,Bonnie I., I/O cell configuration for multiple I/O standards.

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35. Oguri,Takashi, Impedance adjustment circuit and integrated circuit device.

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36. Oguri,Takashi, Impedance adjustment circuit, impedance adjustment method, and semiconductor device.

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37. Chung,Hoe ju; Lee,Jae jun; Kim,Kyu hyoung, Impedance adjustment circuits and methods using replicas of variable impedance circuits.

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38. Kuwahara, Shunji; Fujisawa, Hiroki, Impedance control circuit and semiconductor device including the same.

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39. Huang, Ren-Yuan; Hwang, Yi-Ren, Impedance matching circuit.

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40. Om, Hari, Impedance matching circuit.

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41. Suzuki Azuma,JPX ; Hayakawa Shigeyuki,JPX, Impedance matching circuit, high speed semiconductor integrated circuit employing the same and computer system employing the integrated circuit.

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42. Pilling, David J., In-situ monitor of process and device parameters in integrated circuits.

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43. Pilling, David J.; Talledo, Cesar, In-situ monitor of process and device parameters in integrated circuits.

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44. Kim,Hyun Jin; Jang,Seong Jin; Park,Kwang II; Hwang,Sang Joon; Song,Ho Young; Lee,Ho Kyong; Lee,Woo Jin, Input buffer having a stabilized operating point and an associated method.

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45. Goetting F. Erich ; Frake Scott O. ; Kondapalli Venu M., Input/output buffer supporting multiple I/O standards.

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46. M. Jason Welch ; Brian Cardanha, Integrated circuit with multi-function controlled impedance output drivers.

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47. Pelley,Perry H., Integrated circuit with programmable-impedance output buffer and method therefor.

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48. Yang Seung-Kweon,KRX ; Yoon Yong-Jin,KRX, Integrated driver circuits having independently programmable pull-up and pull-down circuits therein which match load impedance.

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49. Park, Chul-woo; Jun, Young-hyun; Choi, Joo-sun; Hwang, Hong-sun, Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same.

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50. Porter John D. ; Weber Larren Gene, Method and apparatus for circuit variable updates.

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51. Blodgett,Greg A.; Morzano,Christopher K., Method and circuit for off chip driver control, and memory device using same.

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52. Blodgett,Greg A.; Morzano,Christopher K., Method and circuit for off chip driver control, and memory device using same.

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53. Thompson William N. ; Porter John D. ; Weber Larren Gene, Method to find a value within a range using weighted subranges.

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54. Thompson, William N.; Porter, John D.; Weber, Larren Gene, Method to find a value within a range using weighted subranges.

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55. Thompson, William N.; Porter, John D.; Weber, Larren Gene, Method to find a value within a range using weighted subranges.

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56. Thompson, William N.; Porter, John D.; Weber, Larren Gene, Method to find a value within a range using weighted subranges.

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57. Thompson, William N.; Porter, John D.; Weber, Larren Gene, Method to find a value within a range using weighted subranges.

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58. William N. Thompson ; John D. Porter ; Larren Gene Weber, Method to find a value within a range using weighted subranges.

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59. William N. Thompson ; John D. Porter ; Larren Gene Weber, Method to find a value within a range using weighted subranges.

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60. William N. Thompson ; John D. Porter ; Larren Gene Weber, Method to find a value within a range using weighted subranges.

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61. Welch M. Jason ; Cardanha Brian, Multi-function controlled impedance output driver.

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62. Matthews, Lloyd P., Output buffer circuit and method of operation.

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63. Maruyama Shigeru,JPX, Output buffer circuit having a variable output impedance.

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64. Allen,Andrew R.; Arnold,Barry J., Output buffer compensation control.

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65. Koo, Yi-do; Yoo, Chang-sik; Jung, Kee-wook; Kim, Won-chan, Output driver having output current compensation and method of compensating output current.

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66. Masleid, Robert Paul, Power efficient multiplexer.

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67. Masleid, Robert Paul, Power efficient multiplexer.

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68. Choi,Myung Han; Lee,Young Dae; Park,Chul Sung, Programmable impedance control circuit in semiconductor device and impedance range shifting method thereof.

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69. Gary Gibbs ; Manoj B. Roge, Programmable transmission line impedance matching circuit.

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70. Dawe, Geoffrey C., Reconfigurable tunable RF power amplifier.

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71. Nobuaki Otsuka JP, Semiconductor device with impedance controllable output buffer.

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72. Janzen,Jeffrey W.; Morzano,Christopher, System and method for mode register control of data bus operating mode and impedance.

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73. Janzen,Jeffrey W.; Morzano,Christopher, System and method for mode register control of data bus operating mode and impedance.

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74. Martinez,Boris N., Systems and methods for adjusting an output driver.

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75. Nguyen,Huy M., Systems and methods for controlling termination resistance values for a plurality of communication channels.

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76. Nguyen,Huy M., Systems and methods for controlling termination resistance values for a plurality of communication channels.

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77. Vullaganti, Kalyana C., Variable impedance sense architecture and method.

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78. Thompson, William N.; Porter, John D.; Weber, Larren Gene, Variable resistance circuit.

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79. Thompson,William N.; Porter,John D.; Weber,Larren Gene, Variable resistance circuit.

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80. Nakamura, Masayuki; Yoko, Hideyuki, ZQ calibration circuit and a semiconductor device including a ZQ calibration circuit.

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