초록 ▼

A serial port which transmits a start bit of a serial transmission to a non-maskable interrupt terminal of a microprocessor so as to be certain that the microprocessor responds to serial communication. The serial port includes a microprocessor-writable transmit bit connected to the transmit terminal

A serial port which transmits a start bit of a serial transmission to a non-maskable interrupt terminal of a microprocessor so as to be certain that the microprocessor responds to serial communication. The serial port includes a microprocessor-writable transmit bit connected to the transmit terminal of the serial port, a microprocessor-readable receive bit connected to the receive terminal of the serial port, and an NMI enable switch connected between the receive terminal and the NMI pin of the microprocessor. In a receive mode, the NMI enable switch which initially is in a conductive state, transmits the start bit of serial transmissions directly to the NMI pin of the microprocessor causing the microprocessor to interrupt on-going processes. The microprocessor disables the NMI enable register and, after waiting for serial transmission periods between transmitted bits, reads all eight data bits received at the receive terminal from the received bit. Thereafter, the microprocessor re-enables the NMI enable switch and resumes the suspended on-going processes. In a transmit mode, the microprocessor writes a binary 1, corresponding to a start bit, to the transmit bit, causing a transmit signal to be output from the transmit terminal. The microprocessor then transmits the eight bits corresponding to the desired transmit byte, each bit being separated by the appropriate inter-bit serial communication time interval.

대표청구항 ▼

A serial port comprising: a processor adapted to execute process steps for information processing, said processor including a non-maskable interrupt (NMI) pin, which in response to activation of the NMI pin said processor suspends on-going information processing steps and initiates execution of inte

A serial port comprising: a processor adapted to execute process steps for information processing, said processor including a non-maskable interrupt (NMI) pin, which in response to activation of the NMI pin said processor suspends on-going information processing steps and initiates execution of interrupt process steps; a receive bit signal line for carrying a receive bit readable by said processor, said receive bit signal line being connectable to a receive terminal of the serial port and said receive bit being set to a binary 1 or 0 state in correspondence with voltage levels at the receive terminal; an NMI enable switch, connectable between the receive terminal and the NMI pin of said processor, said NMI enable switch being operable under control of said processor so as to transmit signals at the receive terminal to the NMI pin when said NMI enable switch is enabled, and so as to block transmission of signals to the NMI pin when disabled; wherein the interrupt process steps which are initiated by said processor in response to activation of the NMI pin include process steps to (a) disable said NMI enable switch, (b) wait for a serial transmission period and thereafter read a received bit so as to obtain a transmitted data bit, (c) repeat (b) until at least eight transmitted data bits are obtained, (d) assemble the eight transmitted data bits into an 8-bit byte and store the 8-bit byte, (e) enable the NMI enable switch, and (f) resume execution of the suspended on-going information processing steps.