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Method for deriving optimal code schedule sequences from synchronous dataflow graphs 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0400540 (1995-03-07)
발명자 / 주소
  • Powell Douglas B. (San Francisco CA)
출원인 / 주소
  • Cadence Design Systems, Inc. (San Jose CA 02)
인용정보 피인용 횟수 : 66  인용 특허 : 0

초록

A method is disclosed for deriving code schedule sequences for a target code generator from an input ordering of nodes and prime factors of their respective ordered invocation rates from an SDF graph representative of a system. The method involves first creating a loop set for each prime factor wher

대표청구항

A method for deriving code schedule sequences for a target code generator from an input ordering of nodes and prime factors of their respective ordered invocation rates from an SDF graph representative of a system, comprising the steps of: creating a loop set for each prime factor wherein the elemen

이 특허를 인용한 특허 (66)

  1. Werbos, Paul J., 3-brain architecture for an intelligent decision and control system.
  2. Pegatoquet, Alain; Auguin, Michel; Sohier, Olivier, Assembly code performance evaluation apparatus and method.
  3. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
  4. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
  5. Khu,Arthur H., Code optimization method and system.
  6. De Rijck,Bert, Compiling computer programs to exploit parallelism without exceeding available processing resources.
  7. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
  8. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  9. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  10. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  11. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  12. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  13. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
  14. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
  15. Clewis,Fred T.; Sitze,Richard A., Directed non-cyclic graph walking system for data processing and analysis in software application.
  16. Saluja, Sanjeev; Mathur, Anmol, Enhancing mergeability of datapaths and reducing datapath widths responsively to required precision.
  17. Stanfill, Craig W.; Shapiro, Richard; Weiss, Adam; Roberts, Andrew F.; Wholey, III, Joseph Skeffington; Gould, Joel; Kukolich, Stephen A., Executing graph-based program specifications.
  18. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
  19. Lamping John O. ; Kiczales Gregor J. ; Mendhekar Anurag D., High-level loop fusion.
  20. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
  21. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  22. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  23. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
  24. Damron, Peter C., Method and apparatus for inserting data prefetch operations using data flow analysis.
  25. Tirumalai Partha P. ; Subramanian Krishna ; Baylin Boris, Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions.
  26. Bortnikov Vita,ILX ; Mendelson Bilha,ILX ; Novick Mark,ILX ; Roediger Robert Ralph ; Schmidt William Jon ; Shavit-Lottem Inbal,ILX, Method and apparatus for modular reordering of portions of a computer program based on profile data.
  27. Bortnikov Vita,ILX ; Mendelson Bilha,ILX ; Novick Mark,ILX ; Schmidt William Jon ; Shavit-Lottem Inbal,ILX, Method and apparatus for profile-based reordering of program portions in a computer program.
  28. Breternitz ; Jr. Mauricio ; Smith Roger A., Method and apparatus for sequencing computer instruction execution in a data processing system.
  29. Subramanian Krishna ; Baylin Boris, Method and apparatus for time-reversed instruction scheduling with modulo constraints in an optimizing compiler.
  30. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  31. John W. Miller ; John R. Douceur ; Robert P. Fitzgerald, Method and system for incrementally improving a program layout.
  32. Vorbach, Martin, Method for debugging reconfigurable architectures.
  33. Vorbach, Martin, Method for debugging reconfigurable architectures.
  34. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
  35. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
  36. Fox, Kenneth P.; Kolk, Richard A., Method for programming a thermostat.
  37. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
  38. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  39. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  40. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  41. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  42. Leeman, Jr., George B., Methods and apparatus for detecting deadlock in multithreading programs.
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  44. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  46. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  47. Lipton Gary Bruce, Methods, apparatus and computer program products for determining equivalencies between integrated circuit schematics and layouts using color symmetrizing matrices.
  48. Raghavan Vivek ; Zimmerman Brian Allan, Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by.
  49. Raghavan Vivek ; Zimmerman Brian A., Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits using best and worst case delay models for nets therein.
  50. Alur Rajeev ; Yannakakis Mihalis, Model checking of hierarchical state machines.
  51. Rehg,James M.; Knobe,Kathleen, On-line scheduling of constrained dynamic applications for parallel targets.
  52. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  53. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  54. Saluja, Sanjeev; Mathur, Anmol, Procedure for optimizing mergeability and datapath widths of data flow graphs.
  55. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
  56. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
  57. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
  58. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
  59. Vorbach, Martin, Reconfigurable elements.
  60. Vorbach, Martin, Reconfigurable elements.
  61. Vorbach, Martin, Reconfigurable sequencer structure.
  62. Vorbach, Martin, Reconfigurable sequencer structure.
  63. Saluja, Sanjeev; Mathur, Anmol, Reducing datapath widths by rebalancing data flow topology.
  64. Saluja, Sanjeev; Mathur, Anmol, Reducing datapath widths responsively to upper bound on information content.
  65. Vorbach, Martin; Bretz, Daniel, Router.
  66. Rehg,James M.; Knobe,Kathleen, System for computing the optimal static schedule using the stored task execution costs with recent schedule execution costs.
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