$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Surface mountable integrated circuit with conductive vias 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0461643 (1995-06-05)
발명자 / 주소
  • Gaul Stephen J. (Melbourne FL)
출원인 / 주소
  • Harris Corporation (Palm Bay FL 02)
인용정보 피인용 횟수 : 181  인용 특허 : 24

초록

A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. the via has a sidewall oxide 131 and is filled with a conductive material such as metal or do

대표청구항

A surface mountable integrated circuit comprising: a wafer of semiconductor material with first and second surfaces and with integrated circuits formed on the first surface of said wafer; a via comprising a first end on the first surface of the wafer, an elongated passage bounded by a wall of semico

이 특허에 인용된 특허 (24)

  1. Johnson Alfred H. (Poughkeepsie NY), Apertured semi-conductor device mounted on a substrate.
  2. Anthony Thomas R. (Schenectady NY) Cline Harvey E. (Schenectady NY), Deep diode lead throughs.
  3. Bickford Harry R. (57 Sherwood Ave. Ossining NY 10562) Bregman Mark F. (63 Old Washington Rd. Ridgefield CT 06877) Moskowitz Paul A. (R.D. #1 ; Box 343 ; Hunterbrook Rd. Yorktown Heights NY 10598) Pa, Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and pr.
  4. Lorenze ; Jr. ; Robert V. ; White ; William Joseph, Double sided hybrid mosaic focal plane.
  5. Lorenze ; Jr. Robert V. (Westford MA) White William J. (Chelmsford MA), Double sided hybrid mosaic focal plane.
  6. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  7. Simmons Arturo (Garland TX), Focal plane array structure including a signal processing system.
  8. Kurosawa Keiji (Nagano JPX) Yamamoto Kenji (Nagano JPX) Yamashita Mitsuo (Nagano JPX) Mitsui Hisami (Nagano JPX) Miyabara Ayako (Nagano JPX) Miyagawa Kiyotaka (Suzaka JPX) Imura Takayoshi (Nagano JPX, Hollow multilayer printed wiring board.
  9. Soclof, Sidney I., Integrated circuit chip transmission line.
  10. Blocker ; III Truman G. (Richardson TX), Interconnection in multi element planar structures.
  11. Morris ; Raymond A. ; Viola ; Jr. ; Thomas J., Low parasitic capacitance and resistance beamlead semiconductor component and method of manufacture.
  12. Reid Lee R. (Plano TX), Method for fabricating a semiconductor contact and interconnect structure using orientation dependent etching and thermo.
  13. Benjamin James A. (Waukesha WI) Schutten Herman P. (Milwaukee WI) Lade Robert W. (Fort Myers FL), Multi-channel power JFET with buried field shaping regions.
  14. Okabe Kazuya (Furukawa JPX) Kasama Yasuhiko (Izumi JPX) Seki Hitoshi (Izumi JPX) Iwasaki Chisato (Furukawa JPX), Optical sensor including shortcircuit protection having notched electrode regions.
  15. Ng Kwok K. (Union NJ) Sze Simon M. (Berkeley Heights NJ), Packaging microminiature devices.
  16. Abbas Shakir A. (Wappingers Falls NY) Dockerty Robert C. (Highland NY) Poponiak Michael R. (Newburgh NY), Process for forming apertures in silicon bodies.
  17. Kurosawa Keiji (Nagano JPX) Yamamoto Kenji (Nagano JPX) Yamashita Mirsuo (Nagano JPX) Mitsui Hisami (Nagano JPX) Miyabara Ayako (Nagano JPX) Miyagawa Kiyotaka (Suzaka JPX) Imura Takayoshi (Nagano JPX, Process for manufacturing hollow multilayer printed wiring board.
  18. Martyniak Gerald J. (Indianapolis IN), Processes of making two-sided printed circuit boards, with through-hole connections.
  19. Clements Ken (Santa Cruz CA), Semiconductor wafer array.
  20. Clements Ken (Santa Cruz CA), Semiconductor wafer array with electrically conductive compliant material.
  21. Hanes Maurice H. (Murrysville) Clarke Rowland C. (Bell Township) Driver Michael C. (Elizabeth Township PA), Semiconductor wafer with circuits bonded to a substrate.
  22. Tanielian Minas H. (Bellevue WA), Silicon wafers containing conductive feedthroughs.
  23. Grinberg Jan (Los Angeles CA) Jacobson Alexander D. (Los Angeles CA) Chow Kuen (Thousand Oaks CA), Three-dimensionally structured microelectronic device.
  24. Herberg Helmut (Munich DEX), Thyristor with a multi-layer semiconductor body with a pnpn layer sequence and a method for its manufacture with a {111}.

이 특허를 인용한 특허 (181)

  1. Meyer, James W.; Kanski, Cory, Arbitration system and method for memory responses in a hub-based memory system.
  2. Van Hoff, Jay F., Back-side through-hole interconnection of a die to a substrate.
  3. Trezza, John, Back-to-front via process.
  4. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Backside warpage control structure and fabrication method.
  5. Heinen, Katherine G., Ball grid assembly with solder columns.
  6. Adams, Scott G.; Davis, Tim, Boundary isolation for microelectromechanical devices.
  7. Trezza, John, Chip capacitive coupling.
  8. Trezza, John, Chip capacitive coupling.
  9. Trezza, John; Callahan, John; Dudoff, Gregory, Chip connector.
  10. Gillis, John D.; Ni, Wan, Chip guard ring including a through-substrate via.
  11. Trezza, John, Chip spanning connection.
  12. Trezza, John, Chip-based thermo-stack.
  13. Trezza, John, Chip-based thermo-stack.
  14. Trezza, John, Coaxial through chip connection.
  15. Trezza,John, Coaxial through chip connection.
  16. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode.
  17. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  18. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  19. Trezza, John; Callahan, John; Dudoff, Gregory, Contact-based encapsulation.
  20. Oh, Tae Seok; Kim, Jong Hong, Coplanarity inspection system of package and method thereof.
  21. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  22. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  23. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  24. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  25. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  26. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking with leads extending along edges.
  27. Trezza, John, Electrically conductive interconnect system and method.
  28. John A. Trezza ; Gregory K. Dudoff, Electro-optical transceiver system with controlled lateral leakage and method of making it.
  29. John A. Trezza ; Gregory K. Dudoff, Electro-optical transceiver system with controlled lateral leakage and method of making it.
  30. Trezza, John A.; Dudoff, Gregory K., Electro-optical transceiver system with controlled lateral leakage and method of making it.
  31. Trezza, John A.; Dudoff, Gregory K., Electro-optical transceiver system with controlled lateral leakage and method of making it.
  32. Trezza, John A.; Dudoff, Gregory K., Electro-optical transceiver system with controlled lateral leakage and method of making it.
  33. Ebefors, Thorbjorn; Knutsson, Henrik, Electroless metal through silicon via.
  34. Trezza, John; Callahan, John; Dudoff, Gregory, Electronic chip contact structure.
  35. Otremba, Ralf; Schiess, Klaus, Electronic component having at least one vertical semiconductor power transistor.
  36. Williams,Christina K.; Thomas,Rainer E., Electronic packaging including die with through silicon via.
  37. Adams,Scott; Davis,Tim; Miller,Scott; Shaw,Kevin; Chong,John Matthew; Lee,Seung (Chris) Bok, Electrostatic actuator for microelectromechanical systems and methods of fabrication.
  38. Adams,Scott; Davis,Tim; Miller,Scott; Shaw,Kevin; Chong,John Matthew; Lee,Seung Bok (Chris), Electrostatic actuator for microelectromechanical systems and methods of fabrication.
  39. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  40. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  41. Trezza, John, Front-end processed wafer having through-chip connections.
  42. Gaul, Stephen Joseph; Hebert, Francois, Heat conduction for chip stacks and 3-D circuits.
  43. Trezza, John, Heat cycle-able connection.
  44. Gaynes Michael Anthony ; Emerick Alan James ; Puligandla Viswanadham ; Woychik Charles Gerard ; Zalesinski Jerzy Maria, High density integrated circuit packaging with chip stacking and via interconnections.
  45. Gaynes Michael Anthony ; Emerick Alan James ; Puligandla Viswanadham ; Woychik Charles Gerard ; Zalesinski Jerzy Maria, High density integrated circuit packaging with chip stacking and via interconnections.
  46. Gaynes Michael Anthony ; Emerick Alan James ; Puligandla Viswanadham ; Woychik Charles Gerard ; Zalesinski Jerzy Maria, High density integrated circuit packaging with chip stacking and via interconnections.
  47. Dang, Bing; Knickerbocker, John U.; Liu, Yang, Integrated circuit (IC) test probe.
  48. Badehi, Avner, Integrated circuit device.
  49. Badehi, Avner, Integrated circuit device.
  50. Badehi, Avner, Integrated circuit device.
  51. Trezza, John, Inverse chip connector.
  52. Trezza, John, Inverse chip connector.
  53. Trezza, John, Isolating chip-to-chip contact.
  54. Trezza, John, Isolating chip-to-chip contact.
  55. Gacusan, Rodolfo L., Low profile stacked multi-chip package and method of forming same.
  56. Gacusan,Rodolfo L., Low profile stacked multi-chip package and method of forming same.
  57. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
  58. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
  59. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
  60. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
  61. Jobs,Jeffrey R.; Stenglein,Thomas A., Memory hub architecture having programmable lane widths.
  62. Pax, George E.; Greeff, Roy E., Memory module and method having improved signal routing topology.
  63. Pax, George E.; Greeff, Roy E., Memory module and method having improved signal routing topology.
  64. Pax,George E.; Greeff,Roy E., Memory module and method having improved signal routing topology.
  65. Pax,George E.; Greeff,Roy E., Memory module and method having improved signal routing topology.
  66. Pax,George E.; Greeff,Roy E., Memory module and method having improved signal routing topology.
  67. Munch, Ulrich, Metal film protection of the surface of a structure formed on a semiconductor substrate during etching of the substrate by a KOH etchant.
  68. Munch, Ulrich, Metal film protection of the surface of a structure formed on a semiconductor substrate during etching of the substrate by a KOH etchant.
  69. Uzoh, Cyprian Emeka; Monadgemi, Pezhman; Caskey, Terrence; Ayatollahi, Fatima Lina; Haba, Belgacem; Woychik, Charles G.; Newman, Michael, Method and structures for heat dissipating interposers.
  70. Ahrens,Carsten; Huber,Jakob; Seidel,Uwe, Method for fabrication of a contact structure.
  71. Kolb, Stefan; Winkler, Bernhard; Rangelow, Ivo; Blom, Hans-Olof; Bjurstroem, Johan, Method for forming a through via in a semiconductor element and semiconductor element comprising the same.
  72. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  73. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  74. Haba, Belgacem; Mohammed, Ilyas, Method of fabricating stacked assembly including plurality of stacked microelectronic elements.
  75. Haba, Belgacem, Method of fabricating stacked packages with bridging traces.
  76. Haba, Belgacem; Oganesian, Vage, Method of making a stacked microelectronic package.
  77. Haba, Belgacem; Oganesian, Vage, Method of making a stacked microelectronic package.
  78. Takao, Yukihiro, Method of manufacturing ball grid array type semiconductor device.
  79. Dornisch Dieter, Methods for barrier layer formation.
  80. Akram, Salman; Wark, James M.; Hiatt, William Mark, Methods of forming interconnects and semiconductor structures.
  81. Akram, Salman; Wark, James M.; Hiatt, William M., Methods of forming interconnects in a semiconductor structure.
  82. Trezza, John, Mobile binding in an electronic connection.
  83. Hayasaka, Nobuo; Okumura, Katsuya; Sasaki, Keiichi; Matsuo, Mie, Multichip semiconductor device, chip therefor and method of formation thereof.
  84. Hayasaka, Nobuo; Okumura, Katsuya; Sasaki, Keiichi; Matsuo, Mie, Multichip semiconductor device, chip therefor and method of formation thereof.
  85. Hayasaka, Nobuo; Okumura, Katsuya; Sasaki, Keiichi; Matsuo, Mie, Multichip semiconductor device, chip therefor and method of formation thereof.
  86. Hayasaka,Nobuo; Okumura,Katsuya; Sasaki,Keiichi; Matsuo,Mie, Multichip semiconductor device, chip therefor and method of formation thereof.
  87. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip VIAS in stacked chips.
  88. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura, Off-chip vias in stacked chips.
  89. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.
  90. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.
  91. Martin Gruber DE; Gernot Althammer DE, Optical semiconductor component with an optically transparent protective layer.
  92. Chang, Wen-Hsiung, Package process of backside illumination image sensor.
  93. Trezza, John; Callahan, John; Dudoff, Gregory, Patterned contact.
  94. Trezza, John; Frushour, Ross, Pin-type chip tooling.
  95. Trezza, John, Plated pillar package formation.
  96. Trezza, John; Callahan, John; Dudoff, Gregory, Post & penetration interconnection.
  97. Trezza, John, Post-attachment chip-to-chip connection.
  98. Trezza, John, Process for chip capacitive coupling.
  99. Trezza, John, Processed wafer via.
  100. Trezza, John, Processed wafer via.
  101. Trezza, John; Callahan, John; Dudoff, Gregory, Profiled contact.
  102. Haba, Belgacem; Humpston, Giles; Ovrutsky, David; Mirkarimi, Laura, Reconstituted wafer stack packaging with after-applied pad extensions.
  103. Haba, Belgacem; Humpston, Giles; Ovrutsky, David; Mirkarimi, Laura Wills, Reconstituted wafer stack packaging with after-applied pad extensions.
  104. Trezza, John, Redundant optical device array.
  105. Trezza, John, Remote chip attachment.
  106. Trezza, John, Remote chip attachment.
  107. Trezza, John; Frushour, Ross, Rigid-backed, membrane-based chip tooling.
  108. Misra, Abhay; Trezza, John, Routingless chip architecture.
  109. Akram,Salman; Wark,James M.; Hiatt,William M., Selective nickel plating of aluminum, copper, and tungsten structures.
  110. Yuji Tada JP, Semiconductor device.
  111. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device and manufacturing method thereof.
  112. Noma, Takashi; Morita, Yuichi; Yamada, Hiroshi; Okada, Kazuo; Kitagawa, Katsuhiko; Okubo, Noboru; Ishibe, Shinzo; Shinogi, Hiroyuki, Semiconductor device and manufacturing method thereof.
  113. Noma, Takashi; Otsuka, Shigeki; Morita, Yuichi; Okada, Kazuo; Yamada, Hiroshi; Kitagawa, Katsuhiko; Okubo, Noboru; Ishibe, Shinzo; Shinogi, Hiroyuki, Semiconductor device and manufacturing method thereof.
  114. Takao, Yukihiro, Semiconductor device and manufacturing method thereof.
  115. Kitagawa, Katsuhiko; Shinogi, Hiroyuki; Ishibe, Shinzo; Yamada, Hiroshi, Semiconductor device and method of manufacturing the same.
  116. Do, Won Chul; Ko, Yong Jae, Semiconductor device comprising a conductive pad on a protruding-through electrode.
  117. Oliver, Steve; Farnworth, Warren, Semiconductor device having backside redistribution layers.
  118. Oliver, Steve; Farnworth, Warren, Semiconductor device having backside redistribution layers and method for fabricating the same.
  119. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device having through electrodes protruding from dielectric layer.
  120. Akram, Salman; Wark, James M.; Hiatt, William M., Semiconductor device structures including nickel plated aluminum, copper, and tungsten structures.
  121. Akram, Salman; Wark, James M.; Hiatt, William Mark, Semiconductor devices comprising nickel- and copper-containing interconnects.
  122. Yoo, Gil-Sang; Moon, Chang-Rok; Park, Byung-Jun; Kim, Sang-Hoon; Shin, Seung-Hun, Semiconductor devices having backside illuminated image sensors.
  123. Hsieh, Yuan-Chih; Chu, Li-Cheng; Wu, Ming-Tung; Liu, Ping-Yin; Chao, Lan-Lin; Tsai, Chia-Shiung, Semiconductor having a high aspect ratio via.
  124. Hsieh, Yuan-Chih; Chu, Li-Cheng; Wu, Ming-Tung; Liu, Ping-Yin; Chao, Lan-Lin; Tsai, Chia-Shiung, Semiconductor having a high aspect ratio via.
  125. Hsieh, Yuan-Chih; Chu, Richard; Wu, Ming-Tung; Liu, Martin; Chao, Lan-Lin; Tsai, Chia-Shiung, Semiconductor having a high aspect ratio via.
  126. Roh Jae Sung,KRX, Semiconductor memory device and method for fabricating the same.
  127. Kwon, Yong Chai; Ma, Keum-Hee; Lee, Kang-Wook; Lee, Dong-Ho; Han, Seong-il, Semiconductor structure and method for forming the same.
  128. Trezza, John, Side stacking apparatus and method.
  129. Avsian, Osher; Grinman, Andrey; Humpston, Giles; Margalit, Moti, Stack packages using reconstituted wafers.
  130. Haba, Belgacem; Mohammed, Ilyas, Stacked assembly including plurality of stacked microelectronic elements.
  131. Kriman, Moshe; Avsian, Osher; Haba, Belgacem; Humpston, Giles; Burshtyn, Dmitri, Stacked microelectronic assemblies having vias extending through bond pads.
  132. Uzoh, Cyprian Emeka; Monadgemi, Pezhman; Caskey, Terrence; Ayatollahi, Fatima Lina; Haba, Belgacem; Woychik, Charles G.; Newman, Michael, Structures for heat dissipating interposers.
  133. Farnworth Warren M., Surface mount IC using silicon vias in an area array format or same size as die array.
  134. Farnworth Warren M., Surface mount IC using silicon vias in an area array format or same size as die array.
  135. Warren M. Farnworth, Surface mount ic using silicon vias in an area array format or same size as die array.
  136. Jeddeloh, Joseph M., System and method for memory hub-based expansion bus.
  137. Jeddeloh, Joseph M., System and method for memory hub-based expansion bus.
  138. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
  139. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
  140. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
  141. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
  142. Murphy,Tim, System and method for multiple bit optical data transmission in memory systems.
  143. Murphy,Tim, System and method for multiple bit optical data transmission in memory systems.
  144. Taylor,George R., System and method for optically interconnecting memory devices.
  145. Taylor,George R., System and method for optically interconnecting memory devices.
  146. Taylor,George R., System and method for optically interconnecting memory devices.
  147. Taylor,George R., System and method for optically interconnecting memory devices.
  148. Janzen, Jeffery W., System and method for optimizing interconnections of components in a multichip memory module.
  149. Janzen, Jeffery W., System and method for optimizing interconnections of components in a multichip memory module.
  150. Janzen, Jeffery W., System and method for optimizing interconnections of components in a multichip memory module.
  151. Ryan, Kevin J., System and method for optimizing interconnections of memory devices in a multichip module.
  152. Ryan, Kevin J., System and method for optimizing interconnections of memory devices in a multichip module.
  153. Ryan, Kevin J., System and method for optimizing interconnections of memory devices in a multichip module.
  154. James, Ralph; Jeddeloh, Joe, System and method for transmitting data packets in a computer system having a memory hub architecture.
  155. James, Ralph; Jeddeloh, Joe, System and method for transmitting data packets in a computer system having a memory hub architecture.
  156. James,Ralph; Jeddeloh,Joe, System and method for transmitting data packets in a computer system having a memory hub architecture.
  157. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
  158. Trezza, John, Thermally balanced via.
  159. Williams, Charles Kenneth; Bower, Christopher A.; Malta, Dean Michael; Temple, Dorota, Three dimensional interconnect structure and method thereof.
  160. Pogge,H. Bernhard; Yu,Roy, Three-dimensional device fabrication method.
  161. Huang, Min Lung; Wang, Wei Chung; Cheng, Po Jen; Yee, Kuo Chung; Su, Ching Huei; Lo, Jian Wen; Lin, Chian Chi, Three-dimensional package and method of making the same.
  162. Huang, Min-Lung; Wang, Wei-Chung; Cheng, Po-Jen; Yee, Kuo-Chung; Su, Ching-Huei; Lo, Jian-Wen; Lin, Chian-Chi, Three-dimensional package and method of making the same.
  163. Huang,Min Lung; Wang,Wei Chung; Cheng,Po Jen; Yee,Kuo Chung; Su,Ching Huei; Lo,Jian Wen; Lin,Chian Chi, Three-dimensional package and method of making the same.
  164. Zelsacher, Rudolf, Three-dimensionally embodied circuit with electrically connected semiconductor chips.
  165. Trezza,John, Through chip connection.
  166. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  167. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  168. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  169. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  170. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  171. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  172. Dugas, Roger; Trezza, John, Tooling for coupling multiple electronic chips.
  173. Trezza, John, Triaxial through-chip connection.
  174. Trezza, John, Triaxial through-chip connection.
  175. Trezza,John, Triaxial through-chip connection.
  176. Haba, Belgacem; Mohammed, Ilyas; Mirkarimi, Laura; Kriman, Moshe, Wafer level edge stacking.
  177. Trezza, John, Wafer via formation.
  178. Seo, Won Cheol; Cho, Dae Sung, Wafer-level light emitting diode and wafer-level light emitting diode package.
  179. Seo, Won Cheol; Cho, Dae Sung, Wafer-level light emitting diode package and method of fabricating the same.
  180. Seo, Won Cheol; Cho, Dae Sung, Wafer-level light emitting diode package and method of fabricating the same.
  181. Gu, Shiqun; Nowak, Matthew M.; Srinivasan, Anand, Wide input/output memory with low density, low latency and high density, high latency blocks.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로