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Apparatus for encapsulating electronic packages 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B29C-045/02
  • B29C-045/14
출원번호 US-0452130 (1995-05-26)
발명자 / 주소
  • Weber Patrick O. (San Jose CA)
출원인 / 주소
  • Hestia Technologies, Inc. (Sunnyvale CA 02)
인용정보 피인용 횟수 : 62  인용 특허 : 35

초록

A printed wiring board with either a pin grid array, a ball grid array, a land grid array, etc. of electrical contacts is prepared with a heat sink attached in the usual manner. A passage is provided either in the printed wiring board or in the heat sink so that during the transfer molding process,

대표청구항

An apparatus for encapsulating a laminate substrate having a heat sink thereon, comprising: a first mold platen having a recessed portion; a second mold platen for mating with the first mold platen to form a mold cavity adapted to receive the laminate substrate with the heat sink thereon, the second

이 특허에 인용된 특허 (35)

  1. Casati Paolo (Giovanni ITX) De Martiis Carlo C. (Milan ITX) Marchisi Giuseppe (Milan ITX), Apparatus for assembling and resin-encapsulating a heat sink-mounted semiconductor power device.
  2. Moitzger Max (Lodi CA), Apparatus for encapsulating selected portions of a printed circuit board.
  3. Yamamoto Hiroshi (Ibaragi JPX), Arrangement of a semiconductor device for use in a card.
  4. Marrs Robert C. (Scottsdale AZ) Hirakawa Tadashi (Osaka JPX), Ball grid array with via interconnection.
  5. Nakanishi Keiichirou (Kokubunji JPX) Yamada Minoru (Hanno JPX) Yamamoto Masakazu (Kodaira JPX) Ogihara Satoru (Hitachi JPX) Shinohara Hiroichi (Hitachi JPX) Suzuki Hideo (Katsuta JPX), Chip carrier.
  6. Matsumoto Kunio (Yokohama JPX) Oshima Muneo (Yokohama JPX) Sakaguchi Suguru (Chigasaki JPX), Connecting structure for electronic part and method of manufacturing the same.
  7. Shiobara, Toshio; Tomiyoshi, Kazutoshi, Epoxy resin composition.
  8. Juskey Frank J. (Coral Springs FL) Miles Barry M. (Plantation FL) Papageorge Marc V. (Plantation FL), Flip-chip package for integrated circuits.
  9. Prokop Jon S. (Richardson TX), High terminal count integrated circuit device package.
  10. Ackermann Karl-Peter (Niederrohrdorf CHX) Berner Gianni (Baden CHX), Highly integrated circuit and method for the production thereof.
  11. Mullen ; III William B. (Boca Raton FL) Urbish Glenn F. (Coral Springs FL) Freyman Bruce J. (Plantation FL), Leadless pad array chip carrier.
  12. McShane Michael B. (Austin TX) Lin Paul T. (Austin TX), Method for fabricating semiconductor device including package.
  13. Marrs Robert C. (Scottsdale AZ), Method for forming plastic molded package with heat sink for integrated circuit devices.
  14. Ishida Yoshihiro (Tokorozawa JPX) Komatsu Katsuji (Kawagoe JPX) Mimura Seiichi (Kawagoe JPX) Takenouchi Kikuo (Higashimurayama JPX) Yabe Isao (Tokorozawa JPX) Ichikawa Shingo (Sayama JPX) Shimada Yos, Method of making a resin encapsulated pin grid array with integral heatsink.
  15. Ohno Jun-ichi (Yokohama JPX) Fukazawa Koh-ichi (Tokyo JPX) Shindo Masamichi (Yokohama JPX), Method of making a semiconductor device having lead pins and a metal shell.
  16. Juskey Frank J. (Coral Springs FL) Bernardoni Lonnie L. (Coral Springs FL) Freyman Bruce J. (Plantation FL) Suppelsa Anthony B. (Coral Springs FL), Method of making a transfer molded semiconductor device.
  17. Chia Chok J. (Santa Clara CA), Method of molding a pin grid array package.
  18. Fox Leslie R. (Boxborough MA) Wade Paul C. (Shirley MA) Schmidt William L. (Acton MA), Method of packaging and powering integrated circuit chips and the chip assembly formed thereby.
  19. Horney James R. (Cockeysville MD), Method of producing a composite washer assembly.
  20. Freyman Bruce J. (Plantation FL) Juskey Frank J. (Coral Springs FL) Miles Barry M. (Plantation FL), Moisture relief for chip carrier.
  21. Chia Chok J. (Santa Clara CA), Molded pin grid array package GPT.
  22. Sano Takezo (Shiga JPX) Tsuruyoshi Kenichi (Kusatsu JPX), Molding apparatus with retractable preform support pins.
  23. Sakai Kunito (Hyogo JPX) Oshio Kazuharu (Hyogo JPX) Kanegae Hirozoh (Hyogo JPX), Molding machine and method.
  24. Worp Nicolaas H. (Margate FL) Freyman Bruce J. (Plantation FL) Conrath Kurt C. (Lauderhill FL), Overmolded semiconductor package with anchoring means.
  25. Komathu Kathuzi (Kawagoe JPX), Pin grid array package.
  26. Hirata Atsuomi (Nara JPX) Mamiya Hirokuni (Yokkaichi JPX), Plastic molded chip carrier package and method of fabricating the same.
  27. Chia Chok J. (Santa Clara CA), Plastic molded pin-grid-array power package.
  28. Birchler Robert O. (Dallas TX) Williams ; Jr. E. R. (Scottsdale AZ), Process for encapsulating electronic components in plastic.
  29. Palino Douglas F. (Marlboro MA) Fisher Amnon (Newton MA), Programmable ceramic high performance custom package.
  30. Konishi Akira (Kyoto JPX) Wakano Teruo (Kyoto JPX), Semiconductor device and its manufacture.
  31. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX) Wilson Howard P. (Austin TX), Semiconductor device having a pad array carrier package.
  32. Sawaya Hiromichi (Kawasaki JPX), Semiconductor device including a package having a plurality of bumps arranged in a grid form as external terminals.
  33. Heinle Preston J. (Phoenix AZ), Slot transfer molding apparatus and methods.
  34. Juskey Frank J. (Coral Springs FL) Bernardoni Lonnie L. (Coral Springs FL) Swirbel Thomas J. (Davie FL) Miles Barry M. (Plantation FL), Transfer molded semiconductor package with improved adhesion.
  35. Juskey Frank J. (Coral Springs FL) Pennisi Robert W. (Boca Raton FL) Papageorge Marc V. (Plantation FL), Transfer molding compound.

이 특허를 인용한 특허 (62)

  1. Karmazyn, Michael J., Angular encapsulation of tandem stacked printed circuit boards.
  2. Bolken, Todd O.; Peters, David L., Apparatus for encapsulating a multi-chip substrate array.
  3. Bolken,Todd O.; Peters,David L., Apparatus for encapsulating a multi-chip substrate array.
  4. Weber Patrick O., Apparatus for encapsulating electronic packages.
  5. Thummel Steven G., Apparatus for encasing array packages.
  6. Thummel, Steven G., Apparatus for encasing array packages.
  7. Thummel, Steven G., Apparatus for encasing array packages.
  8. Farnworth,Warren M., Apparatus for stereolithographic processing of components and assemblies.
  9. Johnson, Mark S.; Bolken, Todd O., Asymmetric transfer molding method and an asymmetric encapsulation made therefrom.
  10. Johnson, Mark S.; Bolken, Todd O., Asymmetric transfer molding method and an asymmetric encapsulation made therefrom.
  11. Leonard E. Mess, Ball grid array (BGA) encapsulation mold.
  12. Mess Leonard E., Ball grid array (BGA) encapsulation mold.
  13. Mess Leonard E., Ball grid array (BGA) encapsulation mold.
  14. Mess Leonard E., Ball grid array (BGA) encapsulation mold.
  15. Fan,Chun Ho; Lam,Wing Keung; Sze,Ming Wang; Labeeb,Sadak Thamby; McLellan,Neil; Kirloskar,Mohan, Ball grid array package and process for manufacturing same.
  16. Fan,Chun Ho; McLellan,Neil; Tsang,Kwok Cheung, Ball grid array package and process for manufacturing same.
  17. Huang,Cheng Wei; Yao,Kuang Wei, Chip package.
  18. Horiba Yasuhiro,JPX ; Kohmura Toshimi,JPX, Electronic part mounting device.
  19. Mess, Leonard E., Encapsulation method in a molding machine for an electronic device.
  20. Glenn, Thomas P.; Webster, Steven; Hollaway, Roy Dale, Heat spreader with spring IC package.
  21. Glenn, Thomas P.; Webster, Steven; Hollaway, Roy Dale, Heat spreader with spring IC package fabrication method.
  22. Saito, Toshio; Ozeki, Ikuhiko, Insert molding method and mold.
  23. Ahmad,Syed Sajid, Interconnecting substrates for electrical coupling of microelectronic components.
  24. Ahmad,Syed Sajid, Interconnecting substrates for electrical coupling of microelectronic components.
  25. Ma, Xiao-long; Lee, Chun-liang, Manufacturing mold and manufacturing method for color filter.
  26. Bolken, Todd O.; Peters, David L., Method and apparatus for encapsulating a multi-chip substrate array.
  27. LoBianco, Anthony; Greenwood, Jonathon, Method and apparatus for increasing thickness of molded body on semiconductor package.
  28. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  29. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  30. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  31. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  32. Bolken, Todd O.; Peters, David L., Method for encapsulating a multi-chip substrate array.
  33. Thummel Steven G., Method for encasing array packages.
  34. Thummel Steven G., Method for encasing array packages.
  35. Thummel, Steven G., Method for encasing array packages.
  36. Thummel,Steven G., Method for encasing plastic array packages.
  37. Lin,Ying Ren; Tsai,Ho Yi; Huang,Chien Ping; Hsiao,Cheng Hsu, Method for fabricating semiconductor packages.
  38. Appelt Bernd Karl-Heinz ; Boyko Christina Marie ; Farquhar Donald Seton ; Fuerniss Stephen Joseph ; Klodowski Michael Joseph, Method for filling holes in printed wiring boards.
  39. Ahmad, Syed Sajid, Method of Interconnecting substrates for electrical coupling of microelectronic components.
  40. Huang, Chien-Ping, Method of encapsulating a substrate-based package assembly without causing mold flash.
  41. Cobbley,Chad A., Method of encapsulating interconnecting units in packaged microelectronic devices.
  42. Cobbley,Chad A., Method of encapsulating packaged microelectronic devices with a barrier.
  43. Leonard E. Mess, Methods for ball grid array (BGA) encapsulation mold.
  44. Bolken, Todd O., Microelectronic devices and microelectronic die packages.
  45. Tsai, Chung-Che; Shan, Wei-Heng, Mold structure for package fabrication.
  46. Hess, Kevin J.; Lee, Chu-Chung, Molded semiconductor package having a filler material.
  47. Fillion Raymond Albert ; Daum Wolfgang ; Kolc Ronald Frank ; Kuk Donald William ; Wojnarowski Rob Ert John, Multimodule interconnect structure and process.
  48. Johnson, Mark S.; Bolken, Todd O., Overmolding encapsulation process.
  49. Johnson, Mark S.; Bolken, Todd O., Overmolding encapsulation process and encapsulated article made therefrom.
  50. Cobbley, Chad A., Packaged microelectronic devices with interconnecting units.
  51. James, Stephen L.; Cobbley, Chad A., Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices.
  52. James,Stephen L.; Cobbley,Chad A., Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices.
  53. Dumoulin Ann,BEX ; Heerman Marcel,BEX ; Roggen Jean,BEX ; Beyne Eric,BEX ; Hoof Rita van,BEX, Polymer stud grid array.
  54. Ong E. C., Pressure-plate-operative system for one-side injection molding of substrate-mounted integrated circuits.
  55. Wang Kuo K. ; Han Sejin, Pressurized underfill encapsulation of integrated circuits.
  56. Wang Kuo K. ; Han Sejin, Pressurized underfill encapsulation of integrated circuits.
  57. Fan,Chun Ho; Kirloskar,Mohan; McLellan,Neil, Process for fabricating an integrated circuit package with reduced mold warping.
  58. Fan, Chun Ho; Labeeb, Sadak Thamby; Sze, Ming Wang, Process for manufacturing ball grid array package.
  59. Farnworth, Warren M., Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece.
  60. Boutin Lynda,CAX ; Letourneau Martial A.,CAX ; Tetreault Real,CAX, Transfer molding method for forming integrated circuit package.
  61. John J. Lajza, Jr. ; Charles R. Ramsey ; Robert M. Smith, Ultra mold for encapsulating very thin packages.
  62. Lajza ; Jr. John J. ; Ramsey Charles R. ; Smith Robert M., Ultra mold for encapsulating very thin packages.
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