초록 ▼

A system and method for increasing clock edge transition speed and edge phase accuracy. A split clock buffer provides separate controls of a pull-up transistor and a pull-down transistor. The buffer is off (high impedance) between clock edge transitions. Clock edge transition speed is improved by av

A system and method for increasing clock edge transition speed and edge phase accuracy. A split clock buffer provides separate controls of a pull-up transistor and a pull-down transistor. The buffer is off (high impedance) between clock edge transitions. Clock edge transition speed is improved by avoiding the transient condition of a conventional clock buffer where both of the pull-up and pull-down transistors are both on during clock edge transition.

대표청구항 ▼

A method for generating a clock edge from a clock buffer, the buffer receiving an input clock signal having a rising edge and a falling edge, the buffer including a first and second output transistor for generating an output clock signal, the method comprising the steps of: (a) detecting the rising

A method for generating a clock edge from a clock buffer, the buffer receiving an input clock signal having a rising edge and a falling edge, the buffer including a first and second output transistor for generating an output clock signal, the method comprising the steps of: (a) detecting the rising edge of the input clock using an inverter delay and a NAND gate; (b) detecting the falling edge of the input clock using an inverter, an inverter delay, and a AND gate; (c) activating the first output transistor in response to the rising edge, and then deactivating the first output transistor before the falling edge begins; and (d) activating the second output transistor in response to the falling edge, and then deactivating the second transistor before the rising edge begins, such that the activation of the first and second transistors do not overlap, thereby increasing edge transition time.