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Process for manufacturing a semiconductor device by applying a non-single-crystalline material on a sidewall inside of a

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/265
  • H01L-021/20
출원번호 US-0417901 (1995-04-06)
우선권정보 JP-0097257 (1991-04-16); JP-0097244 (1991-04-26); JP-0129506 (1991-05-31)
발명자 / 주소
  • Yuzurihara Hiroshi (Isehara JPX) Miyawaki Mamoru (Tokyo JPX) Ishizaki Akira (Atsugi JPX) Momma Genzo (Hiratsuka JPX) Kochi Tetsunobu (Hiratsuka JPX)
출원인 / 주소
  • Canon Kabushiki Kaisha (Tokyo JPX 03)
인용정보 피인용 횟수 : 64  인용 특허 : 7

초록

An insulated gate type transistor includes a plurality of major electrode regions, a channel region provided between the plurality of major electrode regions, a gate electrode provided on the channel region with a gate insulating film therebetween, and a semiconductor region provided in contact with

대표청구항

A process for manufacturing a semiconductor device, comprising the steps of: a) forming, on a single-crystalline semiconductor region of a substrate, a first insulating film having a first opening portion with a first lateral dimension for exposing the single-crystalline semiconductor region thereth

이 특허에 인용된 특허 (7)

  1. Jastrzebski Lubomir L. (Plainsboro NJ), Fabricating of a CMOS FET with reduced latchup susceptibility.
  2. Kamins Theodore I. (Palo Alto CA) Colinge Jean-Pierre (Palo Alto CA) Marcoux Paul J. (Mountain View CA) Roylance Lynn M. (Los Altos CA) Moll John L. (Palo Alto CA), Method for making patterned implanted buried oxide transistors and structures.
  3. Mizutani Yoshihisa (Tokyo JPX) Takasu Shinichiro (Tokyo JPX), Method of fabricating three-dimensional semiconductor devices utilizing CeO2 and ion-implantation..
  4. Mori, Haruhisa; Ogawa, Tsutomu; Matsumoto, Takashi, Selective epitaxy by beam energy and devices thereon.
  5. Ng Kwok K. (Union NJ) Sze Simon M. (Berkeley Heights NJ), Semiconductor-on-insulator (SOI) devices and SOI IC fabrication method.
  6. Sundaresan Ravishankar (Garland TX), Stacked CMOS sRAM with vertical transistors and cross-coupled capacitors.
  7. Hatano Hiroshi (Yokohama JPX), Stacked MOS device with means to prevent substrate floating.

이 특허를 인용한 특허 (64)

  1. Kuo, Thauming; Vineyard, Mark Kevin; Liang, Weimin Chen, Aldehyde removal.
  2. Tang, Sanh D.; Karda, Kamal M.; Mueller, Wolfgang; Dhir, Sourabh; Kerr, Robert; Hwang, Sangmin; Liu, Haitao, Array of conductive lines individually extending transversally across and elevationally over a mid-portion of individual active area regions.
  3. Rhee,Hwa Sung; Kim,Hyun Suk; Tetsuji,Ueno; Yoo,Jae Yoon; Lee,Seung Hwan; Lee,Ho; Park,Moon han, At least penta-sided-channel type of FinFET transistor.
  4. Noble, Wendell P., Compact SOI body contact link.
  5. Fischer, Mark, DRAM arrays.
  6. Iwanaga, Junko; Takagi, Takeshi; Kanzawa, Yoshihiko; Sorada, Haruyuki; Saitoh, Tohru; Kawashima, Takahiro, FINFET-type semiconductor device and method for fabricating the same.
  7. Stockinger, Michael A.; Hess, Kevin J.; Miller, James W., High frequency interconnect pad structure.
  8. Tashiro, Kazuaki; Kaifu, Noriyuki; Kochi, Tetsunobu; Yuki, Osamu, Image pickup apparatus.
  9. Hamamoto, Osamu; Shimamura, Yoshinori; Kaifu, Noriyuki; Tashiro, Kazuaki; Kochi, Tetsunobu; Yuki, Osamu; Kajiwara, Kenji, Image pickup device, radiation image pickup device and image processing system.
  10. Hamamoto,Osamu; Shimamura,Yoshinori; Kaifu,Noriyuki; Tashiro,Kazuaki; Kochi,Tetsunobu; Yuki,Osamu; Kajiwara,Kenji, Image pickup device, radiation image pickup device and image processing system.
  11. Yukawa, Mikio; Takano, Tamae; Asami, Yoshinobu; Yamazaki, Shunpei; Sato, Takehisa, Memory element and semiconductor device.
  12. Floyd,Philip D.; Sun,Decai; Kubby,Joel A., Method and apparatus for an integrated laser beam scanner.
  13. Floyd, Philip D.; Sun, Decai; Kubby, Joel A., Method and apparatus for an integrated laser beam scanner using a carrier substrate.
  14. Ping, Er-Xuan; McKee, Jeffrey A., Method for forming raised structures by controlled selective epitaxial growth of facet using spacer.
  15. Ping,Er Xuan; McKee,Jeffrey A., Method for forming raised structures by controlled selective epitaxial growth of facet using spacer.
  16. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  17. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  18. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  19. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  20. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  21. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  22. Adkisson,James W.; Agnello,Paul D.; Ballantine,Arne W.; Divakaruni,Rama; Jones,Erin C.; Nowak,Edward J.; Rankin,Jed H., Method of fabricating semiconductor side wall fin.
  23. Adkisson,James W.; Agnello,Paul D.; Ballantine,Arne W.; Divakaruni,Rama; Jones,Erin C.; Nowak,Edward J.; Rankin,Jed H., Method of fabricating semiconductor side wall fin.
  24. Rhee, Hwa-Sung; Kim, Hyun-Suk; Tetsuji, Ueno; Yoo, Jae-Yoon; Lee, Seung-Hwan; Lee, Ho; Park, Moon-han, Method of forming an at least penta-sided-channel type of FinFET transistor.
  25. Ohmi Tadahiro,JPX ; Miyawaki Mamoru,JPX, Method of making a semiconductor device.
  26. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  27. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  28. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  29. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  30. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
  31. Krivokapic, Zoran, Method of manufacturing a semiconductor device having a MESA structure.
  32. Yamazaki, Shunpei, Method of manufacturing a semiconductor device having a gate electrode formed over a silicon oxide insulating layer.
  33. Yamazaki, Shunpei, Method of manufacturing a semiconductor device including thermal oxidation to form an insulating film.
  34. Yamazaki, Shunpei, Method of manufacturing semiconductor device having island-like single crystal semiconductor layer.
  35. Lee Jin-Yuan,TWX ; Liang Mong-Song,TWX ; Liew Boon-Khim,TWX, Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors.
  36. Tang, Sanh D.; Karda, Kamal M.; Mueller, Wolfgang; Dhir, Sourabh; Kerr, Robert; Hwang, Sangmin; Liu, Haitao, Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines.
  37. Grisham, Paul E.; Haller, Gordon A.; Tang, Sanh D., Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells.
  38. Grisham, Paul; Haller, Gordon A.; Tang, Sahn D., Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells.
  39. Kim Il-Kwon,KRX, Methods of forming semiconductor-on-insulator field effect transistors with reduced floating body parasitics.
  40. Yu Sun-il,KRX ; Kang Woo-tag,KRX, Methods of forming semiconductor-on-insulator substrates.
  41. Yamazaki, Shunpei; Ohtani, Hisashi; Koyama, Jun; Fukunaga, Takeshi, Nonvolatile memory and electronic apparatus.
  42. Tamura, Seiichi; Yuzurihara, Hiroshi; Ichikawa, Takeshi; Mishima, Ryuichi, Photoelectric conversion device and manufacturing method thereof.
  43. Yuzurihara, Hiroshi; Mishima, Ryuichi; Watanabe, Takanori; Ichikawa, Takeshi; Tamura, Seiichi, Photoelectric conversion device, method of manufacturing photoelectric conversion device, and image pickup system.
  44. Yuzurihara,Hiroshi; Mishima,Ryuichi; Watanabe,Takanori; Ichikawa,Takeshi; Tamura,Seiichi, Photoelectric conversion device, method of manufacturing photoelectric conversion device, and image pickup system.
  45. Yuzurihara,Hiroshi; Mishima,Ryuichi; Watanabe,Takanori; Ichikawa,Takeshi; Tamura,Seiichi, Photoelectric conversion device, method of manufacturing photoelectric conversion device, and image pickup system.
  46. Fukunaga, Takeshi, Process for production of SOI substrate and process for production of semiconductor device.
  47. Fukunaga, Takeshi, Process for production of SOI substrate and process for production of semiconductor device including the selective forming of porous layer.
  48. Fischer, Mark, Semiconductor constructions, DRAM arrays, and methods of forming semiconductor constructions.
  49. Yamazaki, Shunpei, Semiconductor device.
  50. Takemura, Yasuhiko; Teramoto, Satoshi, Semiconductor device and a method for manufacturing the same.
  51. Takemura, Yasuhiko; Teramoto, Satoshi, Semiconductor device and a method for manufacturing the same.
  52. Takemura, Yasuhiko; Teramoto, Satoshi, Semiconductor device and a method for manufacturing the same.
  53. Iwanaga, Junko; Takagi, Takeshi; Kanzawa, Yoshihiko; Sorada, Haruyuki; Saitoh, Tohru; Kawashima, Takahiro, Semiconductor device and method for fabricating the same.
  54. Yamazaki, Shunpei; Ohtani, Hisashi; Koyama, Jun; Fukunaga, Takeshi, Semiconductor device having buried oxide film.
  55. Anderson, Brent A.; Nowak, Edward J.; Rainey, BethAnn, Semiconductor device having freestanding semiconductor layer.
  56. Taylor, Ted; Yang, Xiawan, Semiconductor devices, assemblies and constructions.
  57. Hirose, Masakazu; Morishita, Fukashi, Semiconductor memory device and manufacturing method of the same.
  58. Hirose,Masakazu; Morishita,Fukashi, Semiconductor memory device and manufacturing method of the same.
  59. Hirose,Masakazu; Morishita,Fukashi, Semiconductor memory device and manufacturing method of the same.
  60. Yamazaki, Shunpei; Koyama, Jun; Miyanaga, Akiharu; Fukunaga, Takeshi, Semiconductor thin film and method of manufacturing the same and semiconductor device and method of manufacturing the same.
  61. Yu Sun-il,KRX ; Kang Woo-tag,KRX, Semiconductor-on-insulator devices having insulating layers therein with self-aligned openings.
  62. Kim Il-Kwon,KRX, Semiconductor-on-insulator field effect transistors with reduced floating body parasitics.
  63. Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Thin film semiconductor device and its manufacturing method.
  64. Ping, Er-Xuan; McKee, Jeffrey A., Vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain.
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