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Hemispherical grained silicon on refractory metal nitride

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/108
출원번호 US-0558164 (1995-11-15)
발명자 / 주소
  • Harshfield Steven T. (Emmett ID)
출원인 / 주소
  • Micron Technology, Inc. (Boise ID 02)
인용정보 피인용 횟수 : 81  인용 특허 : 16

초록

Disclosed is a method of growing hemispherical grained silicon (HSG silicon) over a conductive seed layer. In a preferred embodiment, a contact window is etched in an insulating layer to expose a circuit node, such as an active area of a substrate or a contact plug leading to an active area. A layer

대표청구항

A capacitor plate, the plate comprising: a conductive seed layer electrically connected to an active area of an underlying substrate; and a rough polysilicon layer comprised of a plurality of silicon grains directly contacting the conductive seed layer, the seed layer positioned between the rough po

이 특허에 인용된 특허 (16)

  1. Fazan Pierre (Boise ID) Sandhu Gurtej S. (Boise ID), Dram cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for a capacitive surfac.
  2. Ishigami Takashi (Yokohama JPX) Obata Minoru (Inagi JPX) Kawai Mituo (Yokohama JPX) Satou Michio (Yokohama JPX) Yamanobe Takashi (Yokohama JPX) Maki Toshihiro (Yokohama JPX) Yagi Noriaki (Yokohama JP, Highly purified metal material and sputtering target using the same.
  3. Watanabe Hirohito (Tokyo JPX) Tatsumi Toru (Tokyo JPX), Method for fabricating polycrystalline silicon having micro roughness on the surface.
  4. Dennison Charles H. (Boise ID) Thakur Randhir P. S. (Boise ID), Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon.
  5. Rajeevakumar Thekkemadathil V. (Scarsdale NY), Method for making a high capacitance multi-level storage node for high density TFT load SRAMS with low soft error rates.
  6. Hayashide Yoshio (Hyogo JPX), Method for manufacturing a capacitor having a rough electrode surface.
  7. Han Ki-man (Kyungki KRX) Hwang Chang-gyu (Seoul KRX) Kang Dug-dong (Kyungki KRX) Choi Young-Jae (Kyungki KRX) Yoon Joo-young (Kyungki KRX), Method for manufacturing a capacitor of a semiconductor device.
  8. Tuan Hsiao-Chin (Hsin-Chu TWX) Chou Hsiang-Ming J. (Hsin-Chu TWX), Method for producing a roughened surface capacitor.
  9. Akram Salman (Boise ID) Turner Charles (Chandler AZ) Laulusa Alan (Boise ID), Method of forming a capacitor.
  10. Tatsumi Toru (Tokyo JPX) Sakai Akira (Tokyo JPX), Method of manufacturing polysilicon film including recrystallization of an amorphous film.
  11. Sandhu, Gurtej S.; Doan, Trung T., Method of providing a silicon film having a roughened outer surface.
  12. Tuttle Mark E. (Boise ID), Methods for texturizing polysilicon.
  13. Brown Kris K. (Garden City ID), Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon.
  14. Fazan Pierre (Boise ID) Mathews Viju (Boise ID), Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node.
  15. Lee Ruojia (Boise ID) Gonzalez Fernando (Boise ID), Stacked capacitor doping technique making use of rugged polysilicon.
  16. Wen Duen-Shun (Crompond NY), Textured polysilicon stacked trench capacitor.

이 특허를 인용한 특허 (81)

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  35. Anthony John Mark ; Wallace Robert M. ; Wei Yi ; Wilk Glen, Method of forming a nano-rugged silicon-containing layer.
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  37. Beaman, Kevin L.; Moore, John T., Method of forming a structure over a semiconductor substrate.
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  40. Ramaswamy, Nirmal; Sandhu, Gurtej; Srinivasan, Bhaskar; Smythe, John, Method of forming complex oxide nanodots for a charge trap.
  41. Moore, John T., Method of forming transistors associated with semiconductor substrates comprising forming a nitrogen-comprising region across an oxide region of a transistor gate.
  42. Derderian Garo J., Method of forming tungsten nitride comprising layers using NF.sub.3 as a nitrogen source gas.
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  54. Moore, John T., Methods of forming dielectric materials and methods of processing semiconductor substrates.
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  67. Lu Jiong-Ping, Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density.
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  75. Sandhu, Gurtej; Derderian, Garo J., Semiconductor device with novel film composition.
  76. Doan Trung Tri, Semiconductor processing method of depositing polysilicon.
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  78. Moore, John T., Transistor devices.
  79. Sandhu,Gurtej S.; Moore,John T.; Rueger,Neal R., Transistor structures.
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  81. Ngan Kenny King-Tai ; Mosely Roderick C., Treatment of a titanium nitride layer to improve resistance to elevated temperatures.
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