초록 ▼

There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the proc

There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and an inter-processor communication link allows the processors to communicate with each other for the purpose of establishing operational modes. A parameter memory, accessible via the crossbar switch, is used in conjunction with the communication link for control purposes. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

대표청구항 ▼

A multi-processor system operating in a selected one of a plurality of modes comprising: a plurality of processors, each processor having a data port and a separate instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data

A multi-processor system operating in a selected one of a plurality of modes comprising: a plurality of processors, each processor having a data port and a separate instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port; a plurality of memories greater in number than the number of said plurality of processors, said plurality of memories including an instruction memory corresponding to each of said processors and at least one parameter memory; a switch matrix connected to said data port and said instruction port of each of said plurality of processors and each of said plurality of memories, said switch matrix for selectively and concurrently connecting said data port of each of said processors and said memories in a plurality of operational modes, each of said operational modes including only predetermined particular processor to memory accesses, said switch matrix further connecting said instruction port of each processor to said corresponding instruction memory, said switch matrix connecting any of said plurality of processors for access to said at least one parameter memory regardless of said operational mode; and an interprocessor communication bus connected to each of said processors for transmitting signals from any processor to any other selected processor for effecting changes in said operational mode, said interprocessor communication bus transmitting a parameter read signal from any processor to any other selected processor to read data stored in said at least one parameter memory.