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Diode and semiconductor device having a controlled intrinsic or low impurity concentration region between opposite condu 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
  • H01L-029/94
  • H01L-031/075
  • H01L-031/105
출원번호 US-0348198 (1994-11-28)
우선권정보 JP-0129304 (1990-05-21)
발명자 / 주소
  • Mizutani Hidemasa (Sagamihara JPX) Koizumi Toru (Machida JPX)
출원인 / 주소
  • Canon Kabushiki Kaisha (Tokyo JPX 03)
인용정보 피인용 횟수 : 37  인용 특허 : 2

초록

A diode is provided comprising first and second semiconductor regions. The first semiconductor region is of one conductivity type and the second is of the opposite conductivity type. A third region is provided which is either an intrinsic semiconductor region or a low concentration region. The low c

대표청구항

A diode comprising: an insulating substrate; a first control electrode provided on said insulating substrate; a first insulating layer provided on said first control electrode; a semiconductor layer extending beyond an area over said first control electrode on said insulating substrate, said semicon

이 특허에 인용된 특허 (2)

  1. Eaton ; Jr. Sargent Sheffield (Phillipsburg NJ), Protection circuit for insulated-gate field-effect transistors (IGFETS).
  2. Hayashi Hisao (Kanagawa JPX) Negishi Michio (Kanagawa JPX) Noguchi Takashi (Kanagawa JPX) Ohshima Takefumi (Kanagawa JPX) Hayashi Yuji (Kanagawa JPX) Maekawa Toshikazu (Kanagawa JPX) Matsushita Takes, Thin film MOS transistor having pair of gate electrodes opposing across semiconductor layer.

이 특허를 인용한 특허 (37)

  1. Yamazaki,Shunpei, Electro-optical device.
  2. Yamazaki Shunpei,JPX, Electro-optical device and method for manufacturing the same.
  3. Yamazaki, Shunpei; Takemura, Yasuhiko, Electro-optical device and method for manufacturing the same.
  4. Yamazaki, Shunpei; Takemura, Yasuhiko, Electro-optical device and method for manufacturing the same.
  5. Yamazaki, Shunpei; Takemura, Yasuhiko, Electro-optical device and method for manufacturing the same.
  6. Yamazaki, Shunpei; Takemura, Yasuhiko, Electro-optical device and method for manufacturing the same.
  7. Yamazaki,Shunpei, Electro-optical device and method for manufacturing the same.
  8. Yamazaki,Shunpei, Electro-optical device and method for manufacturing the same.
  9. Yamazaki,Shunpei; Takemura,Yasuhiko, Electro-optical device and method for manufacturing the same.
  10. Yamazaki Shunpei,JPX ; Takemura Yasuhiko,JPX, Electro-optical device having silicon nitride interlayer insulating film.
  11. Yamazaki, Shunpei, Electro-optical device which comprises thin film transistors and method for manufacturing the same.
  12. Yamazaki, Shunpei; Koyama, Jun; Hirakata, Yoshiharu; Fukunaga, Takeshi, Electrooptical device.
  13. Yamazaki, Shunpei; Koyama, Jun; Hirakata, Yoshiharu; Fukunaga, Takeshi, Electrooptical device.
  14. Yamazaki,Shunpei; Koyama,Jun; Hirakata,Yoshiharu; Fukunaga,Takeshi, Electrooptical device.
  15. Rodrigues, Richard A., Epitaxial surge protection device.
  16. Yamazaki, Shunpei, Gate insulated field effect transistor and method of manufacturing the same.
  17. Yamazaki Shunpei,JPX, Gate insulated field effect transistors and method of manufacturing the same.
  18. Lu, JengPing; Apte, Raj B., Gated co-planar poly-silicon thin film diode.
  19. Lu, Jengping; Apte, Raj B., Gated co-planar poly-silicon thin film diode.
  20. Voldman,Steven H.; Mandelman,Jack A., Lateral lubistor structure and method.
  21. Adkisson, James W.; Agnello, Paul D.; Ballantine, Arne W.; Putnam, Christopher S.; Rankin, Jed H., Method and structure of a dual/wrap-around gate field effect transistor.
  22. Burr James B., Partially depleted SOI device having a dedicated single body bias means.
  23. Viscor,Petr; Nielsen,Niels Ole; Delong,Armin; Kolarik,Vladimir, Planar electron emitter (PEE).
  24. Tsunoda,Akira; Yamazaki,Shunpei; Koyama,Jun, Semiconductor device and method for manufacturing the same.
  25. Tsunoda,Akira; Yamazaki,Shunpei; Koyama,Jun, Semiconductor device and method for manufacturing the same.
  26. Yamazaki Shunpei,JPX, Semiconductor device having crystalline silicon clusters.
  27. Shunpei Yamazaki JP; Akiharu Miyanaga JP; Jun Koyama JP; Takeshi Fukunaga JP, Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method.
  28. Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method.
  29. Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method.
  30. Yamazaki,Shunpei; Miyanaga,Akiharu; Koyama,Jun; Fukunaga,Takeshi, Static random access memory using thin film transistors.
  31. Hanzawa, Satoru; Itoh, Kiyoo; Matsuoka, Hideyuki; Terao, Motoyasu; Sakata, Takeshi, Storage device.
  32. Hanzawa,Satoru; Itoh,Kiyoo; Matsuoka,Hideyuki; Terao,Motoyasu; Sakata,Takeshi, Storage device.
  33. Hanzawa,Satoru; Itoh,Kiyoo; Matsuoka,Hideyuki; Terao,Motoyasu; Sakata,Takeshi, Storage device.
  34. Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Thin film semiconductor device and its manufacturing method.
  35. Le Royer, Cyrille; Faynot, Olivier; Clavelier, Laurent, Transistor of the I-MOS type comprising two independent gates and method of using such a transistor.
  36. Tsunoda, Akira; Yamazaki, Shunpei; Koyama, Jun; Osada, Mai, Transistor provided with first and second gate electrodes with channel region therebetween.
  37. Burr James B., Tunable threshold SOI device using back gate and intrinsic channel region.
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