초록 ▼

An ESD protection device is provided which includes a self referencing modulation circuit for controlling its operation. The modulation circuit includes a diode stack coupled to a resistor and further coupled to an inverter powered by the signal pad voltage in one embodiment, or an odd plurality of

An ESD protection device is provided which includes a self referencing modulation circuit for controlling its operation. The modulation circuit includes a diode stack coupled to a resistor and further coupled to an inverter powered by the signal pad voltage in one embodiment, or an odd plurality of series connected inverters powered by the signal pad voltage in an alternate embodiment. The inverter chain is coupled to the ESD clamp. The modulation circuit requires no reference supply voltage to operate. The ESD protection circuit shunts currents associated with ESD events away from ICs as well as clamping I/O pad voltages to acceptable levels during an ESD event.

대표청구항 ▼

An electrostatic discharge (ESD) protection circuit comprising: an ESD clamp device having first and second terminals and a control terminal, said first terminal coupled to a signal line susceptible to ESD and said second terminal coupled to a ground reference; a modulation control device having inp

An electrostatic discharge (ESD) protection circuit comprising: an ESD clamp device having first and second terminals and a control terminal, said first terminal coupled to a signal line susceptible to ESD and said second terminal coupled to a ground reference; a modulation control device having input and output terminals, said output terminal coupled to said control terminal of said ESD clamp device; a reference voltage generator having a first terminal coupled to said input terminal of said modulation control device and a second terminal coupled to said ground reference; a resistor having a first end coupled to said signal line and a second end coupled to said input terminal of said modulation control device and said first terminal of said reference voltage generator, wherein said resistor comprises a PMOS transistor having its gate terminal coupled to its drain terminal.