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Fault tolerant memory system which utilizes data from a shadow memory device upon the detection of erroneous data in a m

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0363132 (1994-12-23)
발명자 / 주소
  • Nielson Michael E. (Broomfield CO) Brant William A. (Boulder CO) Neben Gary (Boulder CO)
출원인 / 주소
  • EMC Corporation (Hopkinton MA 02)
인용정보 피인용 횟수 : 80  인용 특허 : 11

초록

A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory devi

대표청구항

A fault tolerant memory system, comprising: a main memory device, storing data and an associated parity checking code; a shadow memory device, storing data corresponding to the data stored in the main memory; a multiplexer, responsive to a control signal having a first state for coupling data from t

이 특허에 인용된 특허 (11)

  1. Ueno Hitoshi (Zama) Kitano Masahiro (Hiratsuka) Masuda Kenji (Hadano JPX), Access control method for shared duplex direct access storage device and computer system therefor.
  2. Sparks Clyde R. (Riverside CA), Automated concurrent data backup system.
  3. Tsuchiya Kenichi (New Brighton MN), Data protection and error correction, particularly for general register sets.
  4. Beal David G. (Longmont CO) Eifert Fred C. (Louisville CO) Ludlam Henry S. (Longmont CO) Milligan Charles A. (Golden CO) Rudeseal George A. (Boulder CO) Swiatek Paul R. (Lafayette CO), Data storage system for providing redundant copies of data on different disk drives.
  5. Iwami Hiroyuki (Yokohama JPX), Data transfer unit for small computer system with simultaneous transfer to two memories and error detection and rewrite.
  6. Davis Scott H. (Merrimack NH) Goleman William L. (Nashua NH) Thiel David W. (Amherst NH), Digital data management system for maintaining consistency of data in a shadow set.
  7. Fujimura Masanori (Tokyo JPX), Dual data check apparatus.
  8. Kagimasa Toyohiko (Hachioji JPX) Chinone Osamu (Tokyo JPX) Yonenaga Shigeo (Yokohama JPX), Hot stand-by method and computer system for implementing hot stand-by method.
  9. Cesare Brian K. (Kingston NY) Slegel Timothy J. (Staatsburg NY) Whitaker Darell S. (Cottekill NY), Method and apparatus for error recovery in arrays.
  10. Yanai Moshe (Framingham MA) Vishlitzky Natan (Brookline MA) Altersecu Bruno (Newton MA) Castel Daniel (Framingham MA), Method of assuring data write integrity on a data storage device.
  11. Bissett Thomas D. (Derry NH) Bruckert William (Northboro MA) Thirumalai Ajai (Marlboro MA) Amirmokri Jay (Lowell MA), Protocol for transfer of DMA data.

이 특허를 인용한 특허 (80)

  1. Davies,Ian Robert; Maine,Gene; Pecone,Victor Key, Apparatus and method for adopting an orphan I/O port in a redundant storage controller.
  2. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposition of metal oxide and/or low assymmetrical tunnel barrier interpoly insulators.
  3. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators.
  4. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators.
  5. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators.
  6. Maine,Gene, Broadcast bridge apparatus for transferring data to redundant memory subsystems in a storage controller.
  7. Bagley Robert Craig, Cache ram using a secondary controller and switching circuit and improved chassis arrangement.
  8. Ashmore, Paul Andrew; Davies, Ian Robert; Maine, Gene; Vedder, Rex Weldon, Certified memory-to-memory data transfer between active-active raid controllers.
  9. Murray Robert J., Comparator utilizing redundancy.
  10. Stephen L. Scaringella ; Victor W. Tung ; Rudy M. Bauer, Computer storage system controller incorporating control store memory with primary and secondary data and parity areas.
  11. Pecone,Victor Key, Controller data sharing using a modular DMA architecture.
  12. Forbes Leonard ; Reinberg Alan R., DRAM and SRAM memory cells with repressed memory.
  13. Forbes, Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  14. Forbes, Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  15. Forbes,Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  16. Adams Phillip M., Data corruption detection apparatus and method.
  17. Liu, Wei; Kahle, Steven H., Data-aware data flow manager.
  18. Adams Phillip M., Defective floppy diskette controller detection apparatus and method.
  19. Phillip M. Adams, Defective floppy diskette controller detection apparatus and method.
  20. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators.
  21. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  22. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  23. Forbes Leonard ; Ahn Kie Y. ; Noble Wendell P. ; Reinberg Alan R., Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including same.
  24. Nielson Michael E. ; Brant William A. ; Neben Gary, Fault tolerant memory system.
  25. MacLellan, Christopher S.; Walton, John K., Fault tolerant parity generation.
  26. Kramer Alan, Fault-tolerant codes for multi-level memories.
  27. Forbes, Leonard; Eldridge, Jerome M., Flash memory with low tunnel barrier interpoly insulators.
  28. Forbes,Leonard; Eldridge,Jerome M., Flash memory with low tunnel barrier interpoly insulators.
  29. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Graded composition metal oxide tunnel barrier interpoly insulators.
  30. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Graded composition metal oxide tunnel barrier interpoly insulators.
  31. Forbes,Leonard, In service programmable logic arrays with low tunnel barrier interpoly insulators.
  32. Weber,Bret S.; Henry,Russell J.; Gates,Dennis E.; Holt,Keith W., Infiniband isolation bridge merged with architecture of an infiniband translation bridge.
  33. Ichikawa, Takeshi, Information processing device and semiconductor device.
  34. Forbes,Leonard; Eldridge,Jerome M.; Ahn,Kie Y., Integrated circuit memory device and method.
  35. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Low tunnel barrier insulators.
  36. Santeler,Paul A.; Jansen,Kenneth A.; Olarig,Sompong P., Main memory controller adapted to correct corrupted data by xoring corrupted data to directly generate correct data.
  37. Williams, Emrys; Cypher, Robert, Mechanism to improve fault isolation and diagnosis in computers.
  38. Forbes, Leonard, Memory cells having gate structure with multiple gates and multiple materials between the gates.
  39. Thayer,Larry Jay, Memory correction system and method.
  40. Shaw,Mark, Memory mirroring apparatus and method.
  41. Rohleder, Michael; Hay, Gary; Mueller, Stephan; Thanner, Manfred, Memory system with redundant data storage and error correction.
  42. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide nanolaminates.
  43. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide nanolaminates.
  44. Forbes,Leonard; Ahn,Kie Y., Memory utilizing oxide nanolaminates.
  45. Forbes,Leonard; Ahn,Kie Y., Memory utilizing oxide nanolaminates.
  46. Fields, Thomas Austin; Spencer, William Shannon, Method and apparatus for non-volatile memory usage in an ink jet printer.
  47. Arnott Randolph ; Flavin Timothy, Method and apparatus for reliably storing data to be written to a peripheral device subsystem using plural controllers.
  48. Hicks, Raymond Leslie; Kitamorn, Alongkorn; Bailey, Sheldon Ray, Method and system for fault isolation methodology for I/O unrecoverable, uncorrectable error.
  49. Davies, Ian Robert; Pecone, Victor Key, Method for adopting an orphan I/O port in a redundant storage controller.
  50. Davies,Ian Robert; Maine,Gene; Vedder,Rex Weldon, Method for efficient inter-processor communication in an active-active RAID system using PCI-express links.
  51. Hicks, Raymond Leslie; Kitamorn, Alongkorn, Method for managing an uncorrectable, unrecoverable data error (UE) as the UE passes through a plurality of devices in a central electronics complex.
  52. Gupta, Vikas; Tripathi, Ashutosh; Fozard, Bob; Barszczak, Tomasz, Methods for transitioning control between two controllers of a storage system.
  53. Gupta, Vikas; Tripathi, Ashutosh; Fozard, Bob; Barszczak, Tomasz, Methods for transitioning control between two controllers of a storage system.
  54. Adams, Phillip M., Mismatched operation and control correction.
  55. Pecone,Victor Key, Modular architecture for a network storage controller.
  56. Adams,Phillip M., Optimized-incrementing, time-gap defect detection apparatus and method.
  57. Forbes,Leonard, Programmable memory address and decode circuits with low tunnel barrier interpoly insulators.
  58. Forbes,Leonard, Programmable memory address and decode circuits with low tunnel barrier interpoly insulators.
  59. Adams, Phillip M., Programmatic time-gap defect correction apparatus and method.
  60. Adams,Phillip M., Programmatic time-gap defect correction apparatus and method.
  61. Adams, Phillip M., Programmatic time-gap defect detection apparatus and method.
  62. Adams,Phillip M., Programmatic time-gap defect detection apparatus and method.
  63. Ashmore,Paul Andrew; Davies,Ian Robert; Maine,Gene, RAID system for performing efficient mirrored posted-write operations.
  64. Adams,Phillip M., Read-write function separation apparatus and method.
  65. Ashmore, Paul Andrew, Redundant storage controller system with enhanced failure analysis capability.
  66. Forbes, Leonard, SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  67. Forbes,Leonard, SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  68. Davies, Ian Robert, Safe message transfers on PCI-Express link from RAID controller to receiver-programmable window of partner RAID controller CPU memory.
  69. Forbes,Leonard, Service programmable logic arrays with low tunnel barrier interpoly insulators.
  70. Forbes,Leonard, Service programmable logic arrays with low tunnel barrier interpoly insulators.
  71. Adams, Phillip M., Software-hardware read/write integrity verification system.
  72. Adams, Phillip M., Software-hardware welding system.
  73. Adams,Phillip M., Software-hardware welding system.
  74. Don Sawdy ; Arthur L. Rogers, Storage network cabling verification system.
  75. Davies, Ian Robert, System and method for sharing SATA drives in active-active RAID controller system.
  76. Byrd,James M., System and method for verifying error detection/correction logic.
  77. Zumkehr John F. ; Abouelnaga Amir A., Systems and methods for reduced error detection latency using encoded data.
  78. Adams, Philip M., Time-gap defect detection apparatus and method.
  79. Adams, Phillip M., Time-gap defect detection apparatus and method.
  80. Maine,Gene, Transferring data using direct memory access.
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