$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Electronic device for correction of ROM data with a parameter for calculation of position of correction data 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/42
  • G06F-012/06
출원번호 US-0122904 (1993-09-16)
우선권정보 JP-0274943 (1992-09-19)
발명자 / 주소
  • Yamamoto Iwao (Tokyo JPX) Furui Sunao (Kanagawa JPX)
출원인 / 주소
  • Sony Corporation (Tokyo JPX 03)
인용정보 피인용 횟수 : 7  인용 특허 : 40

초록

An electronic device having an integrated structure including central processing means for performing an access control to storage means, a calculation processing, etc., fixed storage means, input means for inputting correction information for correcting information of a specific part stored in the

대표청구항

An electronic device having an integrated structure comprising: central processing means for accessing stored information and calculation processing; fixed storage means for storing information; input means for inputting correction information for correcting a specific part of the information stored

이 특허에 인용된 특허 (40)

  1. Pidsosny Richard A. (Canton MI) Burke Michael J. (Milford MI) Jarvis Mark W. (Unionville CAX), Apparatus and method for correcting microcomputer software errors.
  2. Yamada Shinichiro (Tokyo JA) Ishida Akira (Tokyo JA) Mukai Hisakazu (Musashino JA), Apparatus for accessing an information storage device having defective memory cells.
  3. Crouse Richard S. (Boca Raton FL) Boudreaux Randall P. (Boca Raton FL) Cazzolla ; Jr. John J. (Coral Springs FL), Branch and return on address instruction and methods and apparatus for implementing same in a digital data processing sy.
  4. Santesson Stefan (Lund SEX), Ciphering and deciphering device.
  5. Kaneko Susumu (Kodaira JPX) Kurakazu Keiichi (Tachikawa JPX), Data processor.
  6. Drogichen Daniel P. (West Chester PA), Device for automatic modification of ROM contents by a system selected variable.
  7. Sagane Tomonari (Kanagawa JPX), Electronic apparatus.
  8. Enoki Takashi (Toyokawa JPX) Nakamura Hiroaki (Toyokawa JPX) Nakashima Fujio (Aichi JPX), Function presetting circuit for an audio/video recording and reproducing system.
  9. Kihara ; Toshimasa, Instruction altering system.
  10. Fairchild Peter T. (Woodstock GA) Leininger Joel C. (Boca Raton FL), Link register storage and restore system for use in an instruction pre-fetch micro-processor interrupt system.
  11. Stiffler Jack J. (Concord MA) Budwey Michael J. (Holliston MA) Nolan ; Jr. James M. (Holliston MA), Memory back up system with one cache memory and two physically separated main memories.
  12. Moran John Christian (Broomfield CO), Memory patching circuit.
  13. Divine Charles Hamman (Thornton CO) O\Neill John Francis (Boulder CO), Memory patching circuit with counter.
  14. Divine Charles Hamman (Thornton CO), Memory patching circuit with increased capability.
  15. Divine Charles Hamman (Thornton CO) Moran John Christian (Broomfield CO), Memory patching circuit with repatching capability.
  16. Francis Robert S. (Beaverton OR) Stofer Bruce C. (Hillsboro OR), Memory patching system.
  17. Hilbrink Johan O. (Cincinnati OH), Memory patching system.
  18. Bringol Charles R. (Austin TX) Kroeger ; III Wilbert L. (Austin TX), Memory system with flexible replacement units.
  19. Leger Geary L. (Boise ID) Mauritz Karl H. (Eagle ID) Unrein Chris A. (Boise ID) Voshell Thomas W. (Boise ID), Method and apparatus for storing digital data in off-specification dynamic random access memory devices.
  20. Garber Jonathan F. (Oakland CA), Method for a correlating virtual memory systems by redirecting access for used stock instead of supervisor stock during.
  21. Inrig Scott A. (Ottawa CAX) Chapman Alan S. J. (Kanata both of CAX), Method for providing a substitute memory in a data processing system.
  22. Picon Joaquin (St. Laurent du Var FRX) Poiraud Clement Y. G. (Cagnes sur Mer FRX) Sazbon-Natansohn Daniel (Villeneuve Loubet FRX), Method for storing the control code of a processor allowing effective code modification and addressing circuit therefor.
  23. Miyazawa Hideo (Kawasaki JPX) Komatsu Shigeyuki (Kawasaki JPX) Yoshida Michio (Tokyo JPX) Suzuki Toshiaki (Katano JPX) Miyamoto Akito (Takatsuki JPX) Miyazawa Azuma (Mitaka JPX) Ishimaru Toshiaki (Hi, Microcomputer having ROM to store a program and RAM to store changes to the program.
  24. Miyazawa Azuma (Mitaka JPX) Ishimaru Toshiaki (Hachioji JPX), Microcomputer having a program correction function.
  25. McDonough Kevin C. (Houston TX) Bellay Jeffrey D. (Houston TX), Microcomputer with self-test of microcode.
  26. Sparks Robert W. (Tokyo JPX) Racino Gregory A. (Austin) Gardner Brian R. (Austin TX), Microcontroller having an EPROM with a low voltage program inhibit circuit.
  27. Hoel Jeffrey H. (Los Altos CA) Martinez Eduardo D. (Mountain View CA) Valdes Jacobo (Palo Alto CA), Patchification system.
  28. Wolf Thomas G. (Monroeville PA), Portable programmer-reader unit for programmable time registering electric energy meters.
  29. Patrick, Michael J.; Snider, David M., Program patching in microcomputer.
  30. Powell Robert W. (North Wales PA), Programmable digital memory circuit.
  31. Lee Robert D. (Denton TX), ROM/RAM/ROM patch memory circuit.
  32. Iwai Hidetoshi (Ohme JPX) Ishihara Masamichi (Hamura JPX) Ito Kazuya (Hamura JPX) Arakawa Wataru (Ohme JPX) Nakagome Yoshinobu (Hachioji JPX), Semiconductor integrated device and wiring correction arrangement therefor.
  33. Rouchon RenC. (Paris FRX), Simulation and security device for data entry keyboard.
  34. Heene Mark R. (Austin TX) Menkedick Michael H. (Kokomo IN) Sibigtroth James M. (Round Rock TX) Espinor George L. (Austin TX), Single chip microcomputer with patching and configuration controlled by on-board non-volatile memory.
  35. Yamaguchi Masafumi (Hyogo JPX) Hayashi Kazuo (Hyogo JPX) Kuroki Junji (Hyogo JPX), Single-chip microcomputer with memory patching capability.
  36. Wilburn Darrell L. (Saratoga CA), Software editing instrument.
  37. Clara Jean-Louis (La Colle sur Loup FRX) Jachimczyk Philippe (Saint Jeannet FRX) Le Pennec Jean-Freancois (Nice FRX) Massiera Louis (Levens FRX) Therias Philippe (Nice FRX), System for loading same type adaptors with latest version control codes stored on adaptor memory by selecting the identi.
  38. Mitani Katsuya (Hadano JPX) Sano Toshihiro (Hadano JPX) Nomura Nobutaka (Hadano JPX) Numata Kou (Hadano JPX) Utino Megumi (Hadano JPX), Terminal control system and method of terminal control.
  39. Hirayama Mitsunori (Hyogo JPX) Yamanaka Kimio (Hyogo JPX), Tracing system.
  40. Guterman Daniel C. (Plano TX), User reprogrammable programmed logic array.

이 특허를 인용한 특허 (7)

  1. Neuerburg, Julian, Device and method for bypassing a first program code portion with a replacement program code portion.
  2. Yamamoto Iwao,JPX ; Matsuno Katsumi,JPX, Electronic apparatus and method for patching a fixed information.
  3. Suzuki Takashi,JPX ; Miyazawa Azuma,JPX ; Mizobuchi Koji,JPX, One-chip microcomputer capable of executing correction program and microcomputer capable of correcting ROM.
  4. Han, Dong-Hee, ROM data patch circuit, embedded system including the same and method of patching ROM data.
  5. Yoichi Hirata JP, Semiconductor apparatus.
  6. Yoichi Hirata JP, Semiconductor apparatus.
  7. Vassili Gorshkov ; Richard Efron ; Andrew Jolyon Platt ; Paul William Kohlbrenner, Software debugging method and apparatus.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로