초록 ▼

A programmable timer circuit (18) includes a counter (22) that contains a plurality of sequentially arranged counter stages (22a, 22b). A toggle logic gate (25) is disposed between each sequential pair of counter stages to accept the output signal from the preceding stage and to issue an input signa

A programmable timer circuit (18) includes a counter (22) that contains a plurality of sequentially arranged counter stages (22a, 22b). A toggle logic gate (25) is disposed between each sequential pair of counter stages to accept the output signal from the preceding stage and to issue an input signal to the succeeding counter stage. The logic state of the input signal is determined by the logic state of the preceding output signal and the logic state of a program stage signal from an associated program stage. The logic state of the program signal is determined by the state of a fuse (F) associated with the program stage. Selected fuses can be blown by a programming routine to adjust the time delay between the initiation signal and issuance of the output signal. This sets the counter stages at power-up to a predetermined logic state in which the output signal will be produced with a predetermined time delay when the initiation signal is applied to the integrated circuit. The program routine includes activating the counter stages that will be active at the desired count and issuing a programming signal to burn the fuse associated with the active counter stage.

대표청구항 ▼

A programmable timer circuit which is designed to receive an electric initiation signal and to produce a timer output signal at a predetermined time interval from receipt of the electric initiation signal, the timer circuit comprising: (a) an electrically powered counter comprising a plurality of se

A programmable timer circuit which is designed to receive an electric initiation signal and to produce a timer output signal at a predetermined time interval from receipt of the electric initiation signal, the timer circuit comprising: (a) an electrically powered counter comprising a plurality of sequential counter stages including a first counter stage and a last counter stage for issuing a timer output signal, each counter stage being configured to receive a counter stage input signal having one of an active and an inactive logic state and to issue a counter stage output signal having one of an active and an inactive logic state, the logic state of a counter stage output signal being responsive to a change in the logic state of the counter stage input signal; (b) an electrically powered oscillator for providing a counter stage input signal to the first counter stage; (c) an electrically powered programming circuit comprising (i) a toggle logic gate between each counter stage and the next sequential counter stage for receiving from the preceding counter stage the counter stage output signal and for receiving a program stage signal having one of an active and an inactive logic state, the toggle logic gate issuing to the succeeding counter stage a counter stage input signal having a logic state determined by the logic states of the program stage signal and the counter stage output signal, and (ii) a program stage associated with each toggle logic gate, each program stage being configured to issue to the associated toggle logic gate the program stage signal; (d) electronic initializing means for placing the timer circuit in a logic state determined by the programming circuit prior to incrementing the counter; and (e) power supply means for providing operating power to at least the counter, the oscillator, the programming circuit and the initializing means.