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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0572380 (1995-12-14) |
| 우선권정보 | JP-0200877 (1993-08-12) |
| 발명자 / 주소 |
|
| 출원인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 26 인용 특허 : 0 |
A DRAM operable in a precharge cycle and an activation cycle, includes word lines, bit lines in which a first bit line and a second bit line are included, memory cells located between the first bit line and the second bit line, a first node and a second node through which data in the memory cell is
A semiconductor integrated circuit including a plurality of memory cells arranged in matrix, selected by a plurality of word lines and a plurality of bit lines, operable in a precharge cycle and an activation cycle, comprising: a word line in the word lines for selecting a group of the memory cells;
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