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Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0407309 (1995-03-20)
발명자 / 주소
  • McFarland Harold L. (San Jose CA) Ho Allen P. (Fremont CA)
출원인 / 주소
  • Advanced Micro Devices, Inc. (Sunnyvale CA 02)
인용정보 피인용 횟수 : 87  인용 특허 : 44

초록

A dual-bus architecture that includes a high-speed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus interface (ABI) (60). The ABI is treated as

대표청구항

A method of communicating data between devices in a computer system, the method comprising: providing a bidirectional first bus, said first bus having an architecture wherein a transfer initiated on said first bus includes an address signifying a device with which communication is to be established,

이 특허에 인용된 특허 (44)

  1. Golding Neville L. (Mebane NC), Access control method for DQDB network.
  2. Ward William P. (Poway CA), Advance polling bus arbiter for use in multiple bus system.
  3. Sindhu Pradeep S. (Mountain View) Liencres Bjorn (Palo Alto) Cruz-Rios Jorge (Mountain View) Lee Douglas B. (San Francisco) Chang Jung-Herng (Saratoga) Frailong Jean-Marc (Palo Alto CA), Apparatus and method for a synchronous, high speed, packet-switched bus.
  4. Malmquist Carl A. (Vestal NY) Wilson John D. (Matthews NC), Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis.
  5. Ballatore Daniel (Bar Sur Loup FRX) Huon Simon (Roquefort Les Pins FRX) Munier Jean-Marie (Cagnes Sur Mer FRX), Arbitration device for latching only the highest priority request when the common resource is busy.
  6. Flahive Barry J. (Westford MA) Grady ; III John J. (Woburn MA) Rado Peter J. (Acton MA), Arbitration scheme for a multiported shared functional device for use in multiprocessing systems.
  7. McFarland Harold L. (San Jose CA) Ho Allen P. (Fremont CA), Bus arbitration in a dual-bus architecture where one bus has relatively high latency.
  8. Culler Glen J. (Santa Barbara CA), Bus arbitration system and method.
  9. Skokan Zdenek E. (Redwood City CA) Matheson W. Gordon (Penryn CA), Bus contention resolution method for network devices on a computer network having network segments connected by an inter.
  10. Fischer Lisa L. (Boulder CO) Hanna Stephen D. (Tucson AZ), Bus master with antilockup and no idle bus cycles.
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  12. Ando Takashi (Osaka JPX) Makino Yoshihiro (Osaka JPX), Cassette loading apparatus with improved side plates.
  13. Maresh Anthony J. (Brighton MI) Moore Craig A. (Ypsilanti MI), Computer bus interconnection device.
  14. Zandveld Frederik (Beekbergen NLX) Visser Jeroen M. (Beekbergen NLX), Computer system comprising a data, address and control signal bus which comprises a left bus and a right bus.
  15. McFarland Harold L. (San Jose CA) Ho Allen P. (Fremont CA), Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture.
  16. Banks John D. (Jano) (Palo Alto CA), Data path apparatus for IO adapter.
  17. Banks John D. (Palo Alto CA), Data path apparatus for IO adapter.
  18. Johnson William M. (San Jose CA) Olson Timothy A. (Sunnyvale CA) Dutton Drew J. (Santa Monica CA) Lee Sherman (Palos Verdes Estates CA) Stoenner David W. (El Toro CA), Data transfer controller incorporating direct memory access channels and address mapped input/output windows.
  19. Gallo Paul S. (Watertown MA) Goodman R. W. Benjamin (Hopkinton MA) Krantz Lawrence L. (Marlborough MA) McLoughlin Kathleen A. (Hopkinton MA) Wagner Eric M. (E. Douglas MA), Data transfer operations between two asynchronous buses.
  20. Baxter Leslie A. (Eatontown NJ) Brown Sanford S. (River Plaza NJ), Dual bus communication system.
  21. Pantry William J. (Portland OR) Baumann Burke B. (Glendale AZ), Dual bus system.
  22. Mizuno Kenichi (Yokohama JPX) Morita Takashi (Yokohama JPX) Ikeda Teruo (Yokohama JPX), Duplex data processing system with programmable bus configuration.
  23. Theus John G. (Sherwood OR), Futurebus interrupt subsystem apparatus.
  24. McFarland ; Jr. Harold L. (444 Saratoga Ave. #4G Santa Clara CA 95050), High speed data bus structure.
  25. Roberts Allen W. (Union City CA) McFarland ; Jr. Harold L. (Santa Clara CA) Lau Harlan (Campbell CA), High speed data bus system.
  26. Smith Gehrard J. (Santa Clara CA) Holly Kenneth (San Jose CA), I/O Bus clock.
  27. Banks John D. (J.) (Palo Alto) Karakotsios Kenneth M. (San Jose) Scalise Albert M. (Campbell CA), IO adapter for system and IO buses having different protocols and speeds.
  28. McFarland ; Jr. Harold L. (Santa Clara CA), Improved terminator for high speed data bus.
  29. Bennett Thomas H. (Scottsdale AZ) Carlow Earl F. (Scottsdale AZ) Hepworth Edward C. (Apache Junction AZ) Mensch ; Jr. William D. (Norristown PA) Peddle Charles I. (Norristown PA) Schriber Gene A. (Te, Interface adaptor architecture.
  30. Theus John G. (Sherwood OR) Beachy Jeffrey L. (Wilsonville OR), Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SN.
  31. McFarland Harold L. (San Jose CA), Interrupt control for multiprocessor computer system.
  32. Theus John G. (Sherwood OR) Beachy Jeffrey L. (Wilsonville OR), Lock converting bus-to-bus interface system.
  33. Scalise Albert M. (Campbell CA), Method of arbitration for buses operating at different speeds.
  34. Ludwig Thomas E. (Irvine CA) Craft Thomas W. (Mission Viejo CA), Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus.
  35. Gallagher Andrew M. (Long Beach NY), Multimode resource arbiter providing round robin arbitration or a modified priority arbitration.
  36. Cooper Ronald J. (Raleigh NC) Marsico Mario A. (Cary NC) Pescatore John C. (Durham NC) Sullivan Paul D. (Apex NC), Multiplexed interrupt/DMA request arbitration apparatus and method.
  37. Whittaker Bruce E. (Mission Viejo CA) Barajas Saul (Capistrano Beach CA) Watson Leland E. (Mission Viejo CA), Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests.
  38. Williams Douglas D. (Pepperell MA), Node for servicing interrupt request messages on a pended bus.
  39. Whipple David L. (Braintree MA), Priority apparatus having programmable node dwell time.
  40. Yamasaki Takashi (Itami JPX), Priority control system.
  41. Kriz Thomas A. (Sandy Hook CT), Program controlled bus arbitration for a distributed array processing system.
  42. Narayanan C. Murali (Wheaton IL) Zee Benjamin (Oak Park IL), Programmable memory-based arbitration system for implementing fixed and flexible priority arrangements.
  43. Milia Andrew (Burlington MA) Bahr Richard G. (Cambridge MA), Quasi-fair arbitration scheme with default owner speedup.
  44. Shah Niranjan S. (Escondido CA) Taylor James F. (Escondido CA), System and method for accessing memory connected to different bus and requesting subsystem.

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