초록 ▼

The present invention provides a package for mounting of semiconductor device, wherein: (a) a power layer, a ground layer and a signal layer are laminated via an intermediate layer including an insulating layer, (b) the power layer and the ground layer are each constituted by an inner lead area, an

The present invention provides a package for mounting of semiconductor device, wherein: (a) a power layer, a ground layer and a signal layer are laminated via an intermediate layer including an insulating layer, (b) the power layer and the ground layer are each constituted by an inner lead area, an outer lead area and an electro-conductive area, the inner lead area and the outer lead area being not covered with the intermediate layer and being exposed and the electro-conductive area being interposed between the inner lead area and the outer lead area and covered with the intermediate layer, and (c) substantially all of the electro-conductive area of each of the power layer and the ground layer is constituted by a planar electro-conductive member. In this package, the self-inductances of the power layer and the ground layer are low and the capacitor formed by these layers has a large capacity; therefore, the power line and ground line noise is reduced.

대표청구항 ▼

A packaging for mounting of a semiconductor device, which comprises a power layer, a ground layer and a signal layer, wherein: (a) the power layer, the ground layer and the signal layer are laminated via an intermediate layer including an insulating layer, (b) the power layer and the ground layer ar

A packaging for mounting of a semiconductor device, which comprises a power layer, a ground layer and a signal layer, wherein: (a) the power layer, the ground layer and the signal layer are laminated via an intermediate layer including an insulating layer, (b) the power layer and the ground layer are each constituted by an inner lead area, an outer lead area and an electro-conductive area, the inner lead area and the outer lead area are not covered with the intermediate layer to be exposed and the electro-conductive area is interposed between the inner lead area and the outer lead area and covered with the intermediate layer, (c) substantially all of the electro-conductive area of each of the power layer and the ground layer is constituted by a planar electro-conductive member, and the electro-conductive area has substantially no throughhole, (d) the intermediate layer between the power layer and the ground layer comprises one of the following (1), (2), (3) and (4), (1) a ceramic insulating layer and an inorganic adhesive layer, (2) an organic adhesive layer and an insulating layer present therein, (3) an inorganic adhesive layer or an organic adhesive layer alone, (4) an inorganic adhesive layer or an organic adhesive layer and an insulating layer formed on the surface of at least either of the electro-conductive members present in the electro-conductive areas of the power layer and the ground layer, with a proviso that said inorganic adhesive layer consists essentially of a noble metal brazing alloy or a Cu－O2 type eutectic crystal, (e) the power layer and the ground layer are laminated adjacently via the intermediate layer and adhesive strengths between the power layer and the intermediate layer and between the ground layer and the intermediate layer are each 1 kg/cm or more in terms of 90°peeling strength, and (f) the package is used substantially without being subjected to resin sealing after mounting of the semiconductor device.