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특허 상세정보

MyON담기
내보내기 페이스북 공유 카카오톡 공유

Package for semiconductor device

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H01L-023/52   
미국특허분류(USC) 257/666 ; 257/691 ; 257/692 ; 257/700
출원번호 US-0347484 (1994-12-06)
우선권정보 JP-0079675 (1993-04-06); JP-0315382 (1993-12-15)
국제출원번호 PCT/JP94/00571 (1994-04-06)
§371/§102 date 19941206 (19941206)
국제공개번호 WO-9423448 (1994-10-13)
발명자 / 주소
  • Miyahara Kenichiro (Tokuyama JPX)
출원인 / 주소
  • Tokuyama Corporation (Yamaguchi-ken JPX 03)
인용정보 피인용 횟수 : 46  인용 특허 : 3
초록
▼

The present invention provides a package for mounting of semiconductor device, wherein: (a) a power layer, a ground layer and a signal layer are laminated via an intermediate layer including an insulating layer, (b) the power layer and the ground layer are each constituted by an inner lead area, an outer lead area and an electro-conductive area, the inner lead area and the outer lead area being not covered with the intermediate layer and being exposed and the electro-conductive area being interposed between the inner lead area and the outer lead area and...

대표
청구항
▼

A packaging for mounting of a semiconductor device, which comprises a power layer, a ground layer and a signal layer, wherein: (a) the power layer, the ground layer and the signal layer are laminated via an intermediate layer including an insulating layer, (b) the power layer and the ground layer are each constituted by an inner lead area, an outer lead area and an electro-conductive area, the inner lead area and the outer lead area are not covered with the intermediate layer to be exposed and the electro-conductive area is interposed between the inner l...

이 특허에 인용된 특허 (3)

  1. Mita Mamoru (Hitachi) Takagi Shoji (Hitachi) Aoyama Seigi (Kitaibaraki JPX), High pin count and multi-layer wiring lead frame.
  2. Yoneda Yoshiyuki (Kawasaki JPX) Tsuji Kazuto (Kawasaki JPX) Kasai Junichi (Kawasaki JPX) Sakoda Hideharu (Kawasaki JPX), Semiconductor device and method of producing the same.
  3. McShane Michael B. (Austin TX) Osorio Rolando J. (Manchaca TX), Semiconductor device having a multilayer leadframe with full power and ground planes.

이 특허를 인용한 특허 (46)

  1. Parsons, James D.; Kwak, B. Leo, Adhesion and/or encapsulation of silicon carbide-based semiconductor devices on ceramic substrates.
  2. Parsons,James D.; Kwak,B. Leo, Adhesion and/or encapsulation of silicon carbide-based semiconductor devices on ceramic substrates.
  3. Rutherford Robert B. ; Dudman Richard L., Aircraft de-icing system.
  4. Rutherford Robert B. ; Dudman Richard L., Aircraft de-icing system.
  5. Tellkamp, John P., Aluminum leadframes for semiconductor devices and method of fabrication.
  6. Masuda, Koichiro, Capacitance element, printed circuit board, semiconductor package, and semiconductor circuit.
  7. Thomas H. DiStefano ; John W. Smith, Chip with internal signal routing in external element.
  8. Kraig J. Olejniczak ; Keith C. Burgers ; Simon S. Ang ; Errol V Porter, Conversion of electrical energy from one form to another, and its management through multichip module structures.
  9. Rutherford Robert B., De-ice and anti-ice system and method for aircraft surfaces.
  10. Rutherford Robert B., De-ice and anti-ice system and method for aircraft surfaces.
  11. Antalek, John, Devices and methods for mounting components of electronic circuitry.
  12. Fritsch,Ingrid; Beitle, Jr.,Robert; Aguilar,Zoraida, Electrochemical method for detecting water born pathogens.
  13. Featherby, Michael; DeHaven, Jennifer L., Electronic device packaging.
  14. Michael Featherby ; Jennifer L. DeHaven, Electronic device packaging.
  15. Smith, Joseph O., IC package with integral substrate capacitor.
  16. Kutlu Zafer S., Integrated circuit package having a stiffener dimensioned to receive heat transferred laterally from the integrated circuit.
  17. Fujii Tomoyuki,JPX ; Ushikoshi Ryusuke,JPX, Joined articles, corrosion-resistant joining materials and process for producing joined articles.
  18. Emoto Yoshiaki,JPX, Lead frame and a semiconductor device.
  19. Kim Joong-do,KRX ; Baek Young-ho,KRX ; Bok Kyoung-soon,KRX, Lead frame having a Ni-Mn alloy layer and a Pd layer.
  20. Paulus, Stefan, Leadframe for semiconductor chips and electronic devices and production methods for a leadframe and for electronic devices.
  21. Hierholzer, Martin, Low-inductance semiconductor components.
  22. Mashimoto Yohko,JPX ; Inoue Shuji,JPX ; Kubota Jiro,JPX ; Kuroda Mashahiro,JPX, Method for producing a multilayer interconnection structure.
  23. Kwon, Young-Se; Kim, Kyoung Min, Method of fabricating passive device applied to the three-dimensional package module.
  24. Cohn, Charles; Hawk, Jr., Donald Earl, Method of manufacturing an integrated circuit package.
  25. Martin, John R.; Roberts, Carl M., Methods for packaging and sealing an integrated circuit die.
  26. Fritsch,Ingrid; Henry,Charles Sherman; Bowen,Benjamin P.; Vandaveer,Walter; Bratcher,Nicole, Microfabricated recessed disk microelectrodes: characterization in static and convective solutions.
  27. Fritsch, Ingrid; Beittle, Jr., Robert, Microvolume immunoabsorbant assays with amplified electrochemical detection.
  28. Kwon Oh-Kyong,KRX, Multilayer lead frame structure that reduces cross-talk and semiconductor package using same and fabrication method thereof.
  29. Fritsch,Ingrid; Henry,Charles Sherman; Bowen,Benjamin P.; Vandaveer,Walter R.; Bratcher,Nicole, Multilayer microcavity devices and methods.
  30. DiStefano, Thomas H.; Smith, John W., Off-chip signal routing between multiply-connected on-chip electronic elements via external multiconductor transmission line on a dielectric element.
  31. Martin, John R.; Roberts, Jr., Carl M., Package for sealing an integrated circuit die.
  32. Martin, John R.; Roberts, Jr., Carl M., Package for sealing an integrated circuit die.
  33. Martin,John R.; Roberts, Jr.,Carl M., Package for sealing an integrated circuit die.
  34. Nguyen Toan Dinh ; Johnson Michael T., Power distribution system for semiconductor die.
  35. Kashiwakura, Kazuhiro, Printed wiring board and method of suppressing power supply noise thereof.
  36. Kashiwakura, Kazuhiro, Printed wiring board and method of suppressing power supply noise thereof.
  37. Takahashi, Naoto; Minabe, Yuichiro, Process for producing metallized substrate, and metallized substrate.
  38. Takahashi, Naoto, Production method of metallized substrate.
  39. Fritsch,Ingrid; Beitle, Jr.,Robert; Aguilar,Zoraida, Self-contained microelectrochemical bioassay platforms and methods.
  40. Letterman, Jr., James P.; Fauty, Joseph K.; Yoder, Jay Allen, Semiconductor device and laminated leadframe package.
  41. Busking Erik Bert,NLX ; Sun Yang Ling,NLX ; Visee Maarten,NLX, Semiconductor device having a signal pin with multiple connections.
  42. Ferber, Gottfried; Pelmer, Reimund, Semiconductor module and method for fabricating the semiconductor module.
  43. Yamamoto Yoshiyuki,JPX ; Imai Takahiro,JPX, Semiconductor mounting package.
  44. Zen, Mitsuo, Solder coated material and method for its manufacture.
  45. Kwon, Young-Se; Kim, Kyoung Min, Three-dimensional package module.
  46. Rutherford Robert B. ; Dudman Richard L., Zoned aircraft de-icing system and method.

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