초록 ▼

In a computer system comprising first through N-th processors which are provided with first through N-th processor input/output information transmission paths, respectively, an n-th processor is connected to an (n-1)-th processor, an (n-2)-th processor, an (n+1)-th processor, and an (n+2)-th process

In a computer system comprising first through N-th processors which are provided with first through N-th processor input/output information transmission paths, respectively, an n-th processor is connected to an (n-1)-th processor, an (n-2)-th processor, an (n+1)-th processor, and an (n+2)-th processor, where n represents each of 1 through N, both inclusive. Coupled to the first through the N-th processor input/output information transmission paths and to a system input/output information transmission path for a controlled system, an input/output information path control device connects the system input/output information transmission path to one of the first through the N-th processor input/output information transmission paths. The n-th processor comprises an n-th central processing unit (CPU) for managing the whole of the (n-1)-th processor, an n-th failure detecting circuit for always monitoring an operation state in the (n-1)-th processor, and an n-th input/output information transmission path acquisition control circuit for directing control operation for the input/output information transmission path control device.

대표청구항 ▼

A computer system comprising: first through N-th processors which are provided with first through N-th input/output information transmission paths, respectively, where N represents a positive integer which is not less than two, where n represents each of integers 1 through N, and where: when n is eq

A computer system comprising: first through N-th processors which are provided with first through N-th input/output information transmission paths, respectively, where N represents a positive integer which is not less than two, where n represents each of integers 1 through N, and where: when n is equal to N, an (n+1)-th processor corresponds to the first processor and an (n+2)-th processor corresponds to a second processor, when n is equal to N-1, the n+2)-th processor corresponds to the first processor, when n is equal to N-1, an (n-1)-th processor corresponds to the N-th processor and an (n-2)-th processor corresponds to an (N-1)-th processor, and when n is equal to 2, the (n-2)-th processor corresponds to the N-th processor; and an input/output information transmission path control device coupled to the first through the N-th input/output information transmission paths and to a system input/output information transmission path for a controlled system, said input/output information transmission path control device configured to connect the system input/output information transmission path to one of the first through the N-th input/output information transmission paths, wherein in n-th processor comprises: an n-th central processing unit (CPU) connected to an n-th input/output information transmission path, said (n-1)-th processor, and said (n+1)-th processor, said n-th CPU managing the n-th processor, an n-th failure detecting circuit connected to said (n-1)-th processor and said n-2)-th processor for monitoring an operation state in said (n-1)-th processor, and an n-th input/output information transmission path acquisition control circuit connected to said n-th CPU, said input/output information transmission path control device, said n+1)-th processor, and said (n+2)-th processor, for directing a control operation of said input/output information transmission path control device, and wherein said n-th CPU periodically supplies said (n+1)-th processor with an n-th periodic signal indicative of an operation state of the n-th CPU, said n-th failure detecting circuit monitors the operation state in said (n-1)-th processor by receiving an (n-1)-th periodic signal from said (n-1)-th processor, said n-th failure detecting circuit delivering an n-th monitored result signal to said -th CPU and to an (n-2)-th input/output information transmission path acquisition control circuit in said (n-2)-th processor, said n-th CPU supplies said n-th input/output information transmission path acquisition control circuit with an n-th input/output information transmission path acquisition request signal when said n-th CPU requires acquisition of the system input/output information transmission path, said n-th CPU supplies, in response to the n-th monitored result signal, an n-th input/output information transmission path acquisition prohibited signal to an (n-1)-th input/output information transmission path acquisition control circuit in said (n-1)-th processor, said n-th input/output information transmission path acquisition prohibited signal indicating whether or not said n-th CPU determines that said (n-1)-th processor may acquire the system input/output information transmission path, and said n-th input/output information transmission path acquisition control circuit receives an (n+2)-th monitored result signal, the n-th input/output information transmission path acquisition request signal, and an (n+1)-th input/output information transmission path acquisition prohibited signal, said n-th CPU, an (n+1)-th CPU in said (n+1)-th processor, and said n-th input/output information transmission path acquisition control circuit providing a determination of whether or not the system input/output information transmission path can be acquired by the n-th processor on the basis of the (n+2)-th monitored result signal and the (n+1)-th input/output information transmission path acquisition prohibited signal, said n-th input/output information transmission path acquisition control circuit directing, in response to the n-th input/output information transmission path acquisition request signal and in accordance with the determination, said input/output information transmission path control device to operate control of acquisition of the system input/output information transmission path.