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Digital data processing methods and apparatus for fault detection and fault tolerance 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0309210 (1994-09-20)
발명자 / 주소
  • Horvath Charles J. (Concord MA) Leavitt William I. (Grafton MA) Tetreault Mark D. (Northborough MA) Green Gregory M. (Boxborough MA) Churchill Peter C. (Boxborough MA)
출원인 / 주소
  • Stratus Computer, Inc. (Marlboro MA 02)
인용정보 피인용 횟수 : 70  인용 특허 : 26

초록

A digital data processing device includes a bus for transmitting signals (e.g., data and/or address information) between plural functional units (e.g., a central processing unit and a peripheral controller). A first such unit includes first and second processing sections that concurrently apply to t

대표청구항

A digital data processing device comprising A. bus means for transmitting applied signals between plural functional units, B. a first such functional unit including a first processing section for generating a first signal and for applying a portion thereof to said bus means, C. said first functional

이 특허에 인용된 특허 (26)

  1. Pomfret, Stephen T., Bus for data processing system with fault cycle operation.
  2. Reid Robert (Dunstable MA), Central processing apparatus for fault-tolerant computing.
  3. Dynneson Ronald E. (Brighton MA) Hendrie Gardner C. (Marlboro MA), Computer memory apparatus.
  4. Wolff Kenneth T. (Medway MA) Samson Joseph E. (Dover MA) Baty Kurt F. (Medway MA), Computer peripheral control apparatus.
  5. Waldecker Donald E. (Round Rock TX) Wright Charles G. (Round Rock TX), Data processing system with a plurality of processors accessing a common bus to interleaved storage.
  6. Reid Robert (Dunstable MA), Digital data processing apparatus with pipelined memory cycles.
  7. Hendrie Gardner C. (Marlboro MA) Baty Kurt F. (Medway MA) Dynneson Ronald E. (Brighton MA) Falkoff Daniel M. (Natick MA) Reid Robert (Dunstable MA) Samson Joseph E. (Dover MA) Wolff Kenneth T. (Medwa, Digital data processor apparatus with pipelined fault tolerant bus protocol.
  8. Long William L. (Pembroke MA) Wambach Robert F. (Attleboro MA) Baty Kurt F. (Medway MA) Lamb Joseph M. (Hopedale MA) McNamara John E. (Maynard MA), Digital data processor with fault tolerant peripheral bus communications.
  9. Samson Joseph E. (Dover MA) Wolff Kenneth T. (Medway MA) Reid Robert (Dunstable MA) Hendrie Gardner C. (Marlboro MA) Falkoff Daniel M. (Natick MA) Dynneson Ronald E. (Brighton MA) Clemson Daniel M. (, Digital data processor with high reliability.
  10. Georgiou Christos J. (White Plains NY) Ravn Anders P. (Lyngby DKX), Distributed arbitration for multiple processors.
  11. McDonald John C. (Los Gatos CA) Baichtal James R. (Los Altos CA), Double redundant processor.
  12. Reiff Francis H. (Mannitou Springs CO), Fault tolerant bus.
  13. Hanson David G. (Spring Lake Park MN) Salser Mark A. (Reston VA) Wallace Charles L. (Prior Lake MN), Fault tolerant processor/memory architecture.
  14. Signaigo Robert C. (Oak Lawn IL) Steinlicht Joseph C. (Glen Ellyn IL), Fault tolerant signaling.
  15. Carrubba Francis P. (Sunnyvale CA) Cocke John (Austin TX) Kreitzer Norman H. (Yorktown Heights NY), Hierarchical memory system including separate cache memories for storing data and instructions.
  16. Blum Arnold (Gechingen DEX), Method and apparatus for bus arbitration in a data processing system.
  17. Williams Jeffrey L. (Hopkinton MA), Method and apparatus for detecting selected absence of digital logic synchronism.
  18. Williams Jeffrey L. (Hopkinton MA), Method and apparatus for fault-tolerant computer system having expandable processor section.
  19. Baty Kurt F. (Medway MA) Lamb Joseph M. (Hopedale MA), Method and apparatus for monitoring peripheral device communications.
  20. Jackson Daniel K. (Hillsboro OR), Method and circuit for checking integrated circuit chips.
  21. Stiffler Jack J. (Concord MA) Karp Richard A. (Bedford MA) Nolan ; Jr. James M. (Holliston MA) Budwey Michael J. (Holliston MA) Wallace David A. (Chelmsford MA), Modular computer system.
  22. Danielsen Carl M. (Lake Zurich IL) Dabbish Ezzat A. (Buffalo Grove IL) Puhl Larry C. (Sleepy Hollow IL), Redundant microprocessor control system using locks and keys.
  23. Ossfeldt Bengt E. (lvsjSEX), Stored program controlled real time system including three substantially identical processors.
  24. Irwin John W. (Georgetown TX), System for arbitrating use of I/O bus by co-processor and higher priority I/O units in which co-processor automatically.
  25. Giorcelli Silvano (Turin IT), System for checking two data processors operating in parallel.
  26. Norman John H. (Chandler AZ), Uninterruptable fault tolerant data processor.

이 특허를 인용한 특허 (70)

  1. Eldridge, Keith; Mackay, Brian; Johnson, Mark; Volk, Scott; Burke, Kenneth A.; Meskonis, Paul; Hall, Robert; Dardinski, Steven, Apparatus and method for configuring and editing a control system with live data.
  2. Long,Finbarr Denis; Ardini,Joseph; Kirkpatrick,Dana A.; O'Keeffe,Michael James, Apparatus and methods for fault-tolerant computing using a switching fabric.
  3. Edwards, Jr., John W., Apparatus and methods for identifying bus protocol violations.
  4. Eldridge, Keith; Mackay, Brian; Johnson, Mark; Volk, Scott; Burke, Kenneth A.; Meskonis, Paul; Hall, Robert; Dardinski, Steven, Apparatus for control systems with objects that are associated with live data.
  5. Peleska, Pavel; Schnabel, Dirk, Apparatus for indentifying defects in electronic assemblies.
  6. Garnett Paul J.,GBX, Bus controller.
  7. Bachman, George E.; DeRemer, Robert A.; LeMert, Paul W.; Long, James C.; Weinrich, Steven M.; Wright, Julia, Component object model communication method for a control system.
  8. Funaki, Satoru; Kiyofuji, Yasuhiro; Suenaga, Masashi; Kokura, Shin; Kobayashi, Eiji; Onozuka, Akihiro; Seki, Yusuke; Shimizu, Toshiki; Tahara, Yukiko; Sugimoto, Yuta, Control apparatus and control method.
  9. Eldridge, Keith; Mackay, Brian; Johnson, Mark; Volk, Scott; Burke, Kenneth A.; Meskonis, Paul; Hall, Robert; Dardinski, Steven, Control system configurator and methods with edit selection.
  10. Eldridge, Keith; Mackay, Brian; Johnson, Mark; Volk, Scott; Burke, Kenneth A.; Meskonis, Paul; Hall, Robert; Dardinski, Steven, Control system configurator and methods with object characteristic swapping.
  11. Thibault, Richard L.; Canna, Bruce S.; Couper, Gerald S., Control system methods that transfer control apparatus information over IP networks in web page-less transfers.
  12. Thibault, Richard L.; Canna, Bruce S.; Couper, Gerald S., Control system methods using value-based transfers.
  13. Eldridge, Keith; Mackay, Brian; Johnson, Mark; Volk, Scott; Burke, Kenneth A.; Meskonis, Paul; Hall, Robert; Dardinski, Steven, Control systems and methods with composite blocks.
  14. Eldridge, Keith; Mackay, Brian; Johnson, Mark; Volk, Scott; Burke, Kenneth A.; Meskonis, Paul; Hall, Robert; Dardinski, Steven, Control systems and methods with smart blocks.
  15. Eldridge, Keith; Mackay, Brian; Johnson, Mark; Volk, Scott; Burke, Kenneth A.; Meskonis, Paul; Hall, Robert; Dardinski, Steven, Control systems and methods with versioning.
  16. Mizutani, Fumitoshi; Oda, Shinya, Data processing apparatus and data processing method.
  17. Kagan, Harris D.; Hardin, David, Digital data processing apparatus and methods for improving plant performance.
  18. Horvath Charles J. ; Leavitt William I. ; Tetreault Mark D. ; Green Gregory M. ; Churchill Peter C., Digital data processing methods and apparatus for fault detection and fault tolerance.
  19. Olarig Sompong Paul, Extended-bus functionality in conjunction with non-extended-bus functionality in the same bus system.
  20. Somers, Jeffrey S.; Huang, Wen-Yi; Tetreault, Mark D.; Wegner, Timothy M., Fault-tolerant computer system with voter delay buffer.
  21. Gale, Alan; Bourdin, Christain; Cummings, Gene, Fault-tolerant data transfer.
  22. Suffin, A. Charles; Amato, Joseph S.; Joyce, Paul, Fault-tolerant maintenance bus architecture.
  23. Suffin, A. Charles, Fault-tolerant maintenance bus protocol and method for using the same.
  24. Watabe Toru,JPX ; Sakurai Yasutomo,JPX ; Kishino Takumi,JPX ; Hirose Yoshio,JPX ; Odahara Koichi,JPX ; Nonomura Kazuhiro,JPX ; Takeno Takumi,JPX ; Katoh Shinya,JPX ; Noda Takato,JPX, Information processing system.
  25. Inoue, Hiroaki; Miyazaki, Takashi, Information processor and information processing method.
  26. Manoni,Vittorio, Inherently fail safe processing or control apparatus.
  27. Fenchel Gary Grant, Method and apparatus for downloading a file to a remote unit.
  28. Somers, Jeffrey; Alden, Andrew; Edwards, John, Method and apparatus for efficiently moving portions of a memory block.
  29. Thibault, Richard L.; Canna, Bruce S.; Couper, Gerald S., Method and apparatus for remote process control using applets.
  30. Somers, Jeffrey S.; Tetreault, Mark D.; Wegner, Timothy M., Method and system for upgrading fault-tolerant systems.
  31. Tetreault,Mark, Methods and apparatus for computer bus error termination.
  32. Doll, Benno; Kostadinov, Vladimir; Eldridge, Keith E., Methods and apparatus for control configuration with control objects that are fieldbus protocol-aware.
  33. Kostadinov, Vladimir; Eldridge, Keith E., Methods and apparatus for control configuration with enhanced change-tracking.
  34. Eldridge,Keith; Meskonis,Paul; Hall,Robert; Burke,Kenneth A.; Volk,Scott; Johnson,Mark; Mackay,Brian; Dardinski,Steven, Methods and apparatus for control configuration with versioning, security, composite blocks, edit selection, object swapping, formulaic values and other aspects.
  35. Johnson, Alexander, Methods and apparatus for control using control devices that provide a virtual machine environment and that communicate via an IP network.
  36. Johnson, Alexander; Badavas, Paul C.; Christiansen, T. Eric; Hansen, Peter D.; Kinney, Thomas B.; Keyghobad, Seyamak; Ling, Bo; Thibault, Richard L., Methods and apparatus for control using control devices that provide a virtual machine environment and that communicate via an IP network.
  37. Johnson,Alexander; Badavas,Paul C.; Christiansen,T. Eric; Hansen,Peter D.; Kinney,Thomas B.; Keyghobad,Seyamak; Ling,Bo; Thibault,Richard L., Methods and apparatus for control using control devices that provide a virtual machine environment and that communicate via an IP network.
  38. Dardinski, Steven; Eldridge, Keith; Hall, Robert; Johnson, Mark; MacKay, Brian; Meskonis, Paul; Volk, Scott, Methods and apparatus for controlling object appearance in a process control configuration system.
  39. Galpin,Samuel, Methods and apparatus for fault-detecting and fault-tolerant process control.
  40. Badavas, Paul C.; Hansen, Peter D., Methods and apparatus for object-based process control.
  41. Thibault,Richard L.; Canna,Bruce S.; Couper,Gerald S., Methods and apparatus for remote process control.
  42. Gale Alan Andrew ; Galpin Samuel, Methods and systems for fault-tolerant data transmission.
  43. Thibault, Richard L.; Canna, Bruce S.; Couper, Gerald S., Methods for process control with change updates.
  44. Garnett Paul J.,GBX ; Rowlinson Stephen,GBX ; Oyelakin Femi A.,GBX, Multi-processor system bridge.
  45. Dardinski, Steven; Eldridge, Keith; Hall, Robert; Johnson, Mark; Mackay, Brian; Meskonis, Paul; Volk, Scott, Process control configuration system with connection validation and configuration.
  46. Dardinski,Steven; Eldridge,Keith; Hall,Robert; Johnson,Mark; McKay,Brian; Meskonis,Paul; Volk,Scott, Process control configuration system with connection validation and configuration.
  47. Dardinski,Steven; Eldridge,Keith; Hall,Robert; Johnson,Mark; McKay,Brian; Meskonis,Paul; Volk,Scott, Process control configuration system with parameterized objects.
  48. Khuti, Bharat; Coleman, Clayton; Rath, David; Rakaczky, Ernest; Leslie, Jim; Peralta, Juan; Simpson, George, Process control methods and apparatus for intrusion detection, protection and network hardening.
  49. Richard L. Thibault, Process control system and method with automatic fault avoidance.
  50. Thomas B. Kinney ; T. Eric Christiansen ; Peter D. Hansen ; Bo Ling ; Paul C. Badavas ; Richard L. Thibault, Process control system and method with improved distribution, installation and validation of components.
  51. Thibault, Richard L.; Canna, Bruce S.; Couper, Gerald S., Process control system with networked digital data processors and a virtual machine environment.
  52. Takita Masatoshi,JPX ; Ohnishi Kazuei,JPX ; Saito Takamitsu,JPX, Redundant apparatus.
  53. James L. Petivan ; Jonathan K. Lundell ; Don C. Lundell, Redundant clock system and method for use in a computer.
  54. Ryan, Jr., Lawrence H., Second transfer logic causing a first transfer logic to check a data ready bit prior to each of multibit transfer of a continous transfer operation.
  55. Ninomiya, Tatuya; Masuzaki, Hidefumi; Kurosawa, Hiroyuki; Takahashi, Naoya; Inoue, Yasuo; Iwasaki, Hidehiko; Hoshino, Masayuki; Isono, Soichi, Storage system.
  56. Ninomiya,Tatuya; Masuzaki,Hidefumi; Kurosawa,Hiroyuki; Takahashi,Naoya; Inoue,Yasuo; Iwasaki,Hidehiko; Hoshino,Masayuki; Isono,Soichi, Storage system having a semiconductor memory device which stores data and parity data permanently.
  57. Ninomiya,Tatuya; Masuzaki,Hidefumi; Kurosawa,Hiroyuki; Takahashi,Naoya; Inoue,Yasuo; Iwasaki,Hidehiko; Hoshino,Masayuki; Isono,Soichi, Storage system having data format conversion function.
  58. Ninomiya, Tatuya; Masuzaki, Hidefumi; Kurosawa, Hiroyuki; Takahashi, Naoya; Inoue, Yasuo; Iwasaki, Hidehiko; Hoshino, Masayuki; Isono, Soichi, Storage system having plural buses.
  59. Ninomiya Tatuya,JPX ; Masuzaki Hidefumi,JPX ; Kurosawa Hiroyuki,JPX ; Takahashi Naoya,JPX ; Inoue Yasuo,JPX ; Iwasaki Hidehiko,JPX ; Hoshino Masayuki,JPX ; Isono Soichi,JPX, Storage system realizing scalability and fault tolerance.
  60. Jain, Palkesh; Bansal, Virendra; Gulati, Rahul, System and method for false pass detection in lockstep dual core or triple modular redundancy (TMR) systems.
  61. Graham, Simon P., System and method for operating a SCSI bus with redundant SCSI adaptors.
  62. Nelvin, Robert E.; Tetreault, Mark D.; Alden, Andrew; Dolaty, Mohsen; Edwards, Jr., John W.; Kement, Michael W.; MacLeod, John R., System and method for operating a system with redundant peripheral bus controllers.
  63. Fiorentino, Richard D.; Kaman, Charles H.; Troiani, Mario; Muench, Erik, System for cross-host, multi-thread session alignment.
  64. Zumkehr John F. ; Abouelnaga Amir A., Systems and methods for control flow error detection in reduced instruction set computer processors.
  65. Rovaglio, Maurizio; Scheele, Tobias, Systems and methods for immersive interaction with actual and/or simulated facilities for process, environmental and industrial control.
  66. Zumkehr John F. ; Abouelnaga Amir A., Systems and methods for reduced error detection latency using encoded data.
  67. Bansal,Akash; Sobelman,Michael; Li,Simon; Draper,Donald A., Through-core self-test with multiple loopbacks.
  68. Bressoud Thomas C. ; Ahern John E. ; Birman Kenneth P. ; Cooper Robert C. B. ; Glade Bradford B. ; Schneider Fred B. ; Service John D., Transparent fault tolerant computer system.
  69. Petivan James L. ; Lundell Jonathan K. ; Lundell Don C., Triple modular redundant computer system.
  70. Petivan James L. ; Lundell Jonathan K. ; Lundell Don C., Triple modular redundant computer system and associated method.
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