IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0428817
(1995-04-24)
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발명자
/ 주소 |
- Branco Richard G. (Westmont NJ) Monastra Edward J. (Voorhees NJ) Ovadia David J. (New York NY)
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출원인 / 주소 |
- Martin Marietta Corp. (Moorestown NJ 02)
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인용정보 |
피인용 횟수 :
5 인용 특허 :
7 |
초록
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A digital signal processor (24) includes a plurality of vector processors (212x), each of which is made up of a group of, for example, six signal processors (214x). Each signal processor includes Local 1 and Local 2 ports (201, 203), and the Local 1 port of one processor of a group is coupled by a p
A digital signal processor (24) includes a plurality of vector processors (212x), each of which is made up of a group of, for example, six signal processors (214x). Each signal processor includes Local 1 and Local 2 ports (201, 203), and the Local 1 port of one processor of a group is coupled by a path (218) to the Local 2 port of another processor, so the group forms a ring. Each signal processor (214) also includes a memory (234), an arithmetic processor (232), and a switcher (230) for making internal interconnections among the ports, and also includes a switcher control (364, 366). At least one of the signal processors (214) of each group is of a type including a further external port (206), by which data can be coupled by a path (105) to and from the group. The signal processors of each group can be interconnected for serial or parallel processing, all under the control of a group controller (216) associated with each vector processor.
대표청구항
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An apparatus for processing signals in serial pipeline fashion or in parallel fashion through a plurality of processors, said apparatus comprising: first, second and third processors, each including an input port and an output port, for processing signals; first, second and third memories, for tempo
An apparatus for processing signals in serial pipeline fashion or in parallel fashion through a plurality of processors, said apparatus comprising: first, second and third processors, each including an input port and an output port, for processing signals; first, second and third memories, for temporarily storing and retrieving data; first, second and third switching means coupled to said first, second and third processors, respectively, and to said first, second and third memories, respectively, each of said first, second and third switching means including local 1 and local 2 input/output ports, at least one of said first, second and third switching means including an external connection input-output port, said first switching means being for, in a first direction in a first mode of operation, coupling signals from said local 1 port of said first switching means to said input port of said first processing means, and from said output port of said first processing means to said first memory means; for, in a second direction in a first mode of operation, coupling signals from said local 2 port to said input port of said first processing means, and from said output port of said first processing means to said local 1 port; for, in a first direction in a second mode of operation, coupling signals from said local 1 port of said first switching means to said input port of said first processing means, and from said output port of said first processing means to said local 2 port of said first switching means; for, in a second direction in said second mode of operation, coupling signals from said local 2 port of said first switching means to said input port of said first processing means, and from said output port of said first processing means to said local 1 port of said first switching means; for, in a third mode of operation, for coupling signals from said first memory means to said input port of said first processing means, and from said output port of said first processing means to said first memory means; for, in a first direction of a fourth mode of operation, coupling signals from said first memory means to said input port of said first processing means, and from said output port of said first processing means to said local 1 port of said first switching means; for, in a second direction of a fourth mode of operation, coupling signals from said first memory means to said input port of said first processing means, and from said output port of said first processing means to said local 2 port of said first switching means; for, in a first direction of a fifth mode of operation, coupling signals from said external connection port of said first switching means, if such a port exists, to said first memory means; and for, in a second direction of said fifth mode of operation, coupling signals to said external connection port of said first switching means, if such a port exists, from said first memory means; said second switching means being for, in a first direction in a first mode of operation, coupling signals from said local 1 port of said second switching means to said input port of said second processing means, and from said output port of said second processing means to said second memory means; for, in a second direction in said first mode of operation, coupling signals from said local 2 port of said second switching means to said input port of said second processing means, and from said output port of said second processing means to said local 1 port of said second switching means; for, in a first direction in a second mode of operation, coupling signals from said local 1 port of said second switching means to said input port of said second processing means, and from said output port of said second processing means to said local 2 port of said second switching means; for, in a second direction in said second mode of operation, coupling signals from said local 2 port of said second switching means to said input port of said second processing means, and from said output port of said second processing means to said local 1 port of said second switching means; for, in a third mode of operation, coupling signals from said second memory means to said input port of said second processing means, and from said output port of said second processing means to said second memory means; for, in a first direction of a fourth mode of operation, coupling signals from said second memory means to said input port of said second processing means, and from said output port of said second processing means to said local 1 port of said second switching means; for, in a second direction of a fourth mode of operation, coupling signals from said second memory means to said input port of said second processing means, and from said output port of said second processing means to said local 2 port of said second switching means; for, in a first direction of a fifth mode of operation, coupling signals from said external connection port of said second switching means, if such a port exists, to said second memory means; and for, in a second direction of said fifth mode of operation, coupling signals to said external connection port of said second switching means, if such a port exists, from said second memory means; said third switching means being for, in a first direction in a first mode of operation, coupling signals from said local 1 port of said third switching means to said input port of said third processing means, and from said output port of said third processing means to said third memory means; for, in a second direction in said first mode of operation, coupling signals from said local 2 port of said third switching means to said input port of said third processing means, and from said output port of said third processing means to said local 1 port of said third switching means; for, in a first direction in a second mode of operation, coupling signals from said local 1 port of said third switching means to said input port of said third processing means, and from said output port of said third processing means to said local 2 port of said third switching means; for, in a second direction in said second mode of operation, coupling signals from said local 2 port of said third switching means to said input port of said third processing means, and from said output port of said third processing means to said local 1 port of said third switching means; for, in a third mode of operation, coupling signals from said third memory means to said input port of said third processing means, and from said output port of said third processing means to said third memory means; for, in a first direction of a fourth mode of operation, coupling signals from said third memory means to said input port of said third processing means, and from said output port of said third processing means to said local 1 port of said third switching means; for, in a second direction of a fourth mode of operation, coupling signals from said third memory means to said input port of said third processing means, and from said output port of said third processing means to said local 2 port of said third switching means; for, in a first direction of a fifth mode of operation, coupling signals from said external connection port of said third switching means, if such a port exists, to said third memory means; and for, in a second direction of said fifth mode of operation, coupling signals to said external connection port of said third switching means, if such a port exists, from said third memory means; interconnection means coupled to said local 1 and local 2 input/output ports of said first, second, and third switching means, for coupling said local 2 input/output port of said first switching means to said local 1 input/output port of said second switching means, for coupling said local 2 input/output port of said second switching means to said local 1 input/output port of said third switching means, and for coupling said local 2 input/output port of said third switching means to said local 1 input/output port of said first switching means.
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