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Simplified dual damascene process for multi-level metallization and interconnection structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0320516 (1994-10-11)
발명자 / 주소
  • Huang Richard J. (Milpitas CA) Hui Angela (Milpitas CA) Cheung Robin (Cupertino CA) Chang Mark (Los Altos CA) Lin Ming-Ren (Cupertino CA)
출원인 / 주소
  • Advanced Micro Devices, Inc. (Sunnyvale CA 02)
인용정보 피인용 횟수 : 268  인용 특허 : 0

초록 ▼

A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer thereb

대표청구항 ▼

A method of forming a conductive wiring and a via on a substrate comprising: (a) forming a first insulative layer on said substrate; (b) forming an etch stop layer on said first insulative layer; (c) forming a second insulative layer on said etch stop layer; (d) forming an opening in said second ins

이 특허를 인용한 특허 (268)

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