[특허]Multi-processor computer system having dual memory subsytems for enabling concurrent memory access thereto by more than

Multi-processor computer system having dual memory subsytems for enabling concurrent memory access thereto by more than 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-013/16 G06F-013/36
출원번호	US-0362389 (1994-12-22)
발명자 / 주소	Ingerman Donald (Boca Raton FL)
출원인 / 주소	International Business Machines Corporation (Armonk NY 02)
인용정보	피인용 횟수 : 18 인용 특허 : 0

초록 ▼

A multi-processor information handling system employs multiple multi-processor bus/memory subsystem groups wherein the processors may operate programs concurrently, and concurrent memory operations may be performed with the multiple memory subsystems via the associated multi-processor buses responsive to address location directors. The invention expands the system bandwidth and improves overall multi-processor information handling system performance.

대표청구항 ▼

A multi-processor information handling system, comprising: (a) a first processor; (b) a second processor; (c) it first memory subsystem having a first set of memory addresses; (d) it second memory subsystem having a second set of memory addresses; (e) a first multi-processor bus for transferring information: (1) between said first processor and said first memory subsystem; and (2) between said second processor and said first memory subsystem; (f) a second multi-processor bus for transferring information: (1) between said first processor and said second memory subsystem; and (2) between said second processor and said second memory subsystem; said first and second multi-processor buses using independent arbitration protocols; (g) a first processor address location director configured for directing first processor memory operations to said first memory subsystem and to said second memory subsystem; (h) it first processor first multi-processor bus interface unit connected between said first processor and said first multi-processor bus, and being configured for accessing said first set of memory addresses of said first memory subsystem responsive to said first processor address location actor, wherein information for performing first processor memory operations is transferred between said first processor and said first memory subsystem; (i) a first processor second multi-processor bus interface unit connected between said first processor and said second multi-processor bus, and being configured for accessing said second set of memory addresses of said second memory subsystem responsive to said first processor address location director, wherein information performing first processor memory operations is transferred between said first processor and said second memory subsystem; (j) a second processor address location director configured for directing second processor memory operations to said first memory subsystem and to said second memory subsystem, said first and second processor address location directors each comprising a programmable microprocessor into which may be programmed an address director program and a memory subsystem address directory; (k) a second processor first multi-processor bus interface unit connected between said second processor and said first multi-processor bus, and being configured for accessing said first set of memory addresses of said first memory subsystem responsive to said second processor address location director, wherein information for performing second processor memory operations is transferred between said second processor and said first memory subsystem independently and concurrently while information for performing first processor memory operations is transferred between said first processor and said second memory subsystem; and (l) a second processor second multi-processor bus interface unit connected between said second processor and said second multi-processor bus, and being configured for accessing said second set of memory addresses of said second memory subsystem responsive to said second processor address location director, wherein information for performing second processor memory operations is transferred between said second processor and said second memory subsystem independently and concurrently while information for performing first processor memory operations is transferred between said first processor and said first memory subsystem.

이 특허를 인용한 특허 (18)

Greenspan Steven Jay ; Scalzi Casper Anthony ; Plambeck Kenneth Ernest, Blocking symbol control in a computer system to serialize accessing a data resource by simultaneous processor requests.
상세보기
Louzoun, Eliel; Ben-Shahar, Yifat, Communication between two embedded processors.
상세보기
Mergard James O., Communication system which in a first mode supports concurrent memory acceses of a partitioned memory array and in a se.
상세보기
Bailey,Robert L; Howard,Brian D; Wynne,Lesley B, Dynamically allocating devices to buses.
상세보기
Matter,Eugene P.; Ganesan,Ramkarthik, Memory adapted to provide dedicated and or shared memory to multiple processors and method therefor.
상세보기
Foster Eric M. ; Herndon Steven B. ; Ngai Chuck H., Memory interface for functional unit of integrated system allowing access to dedicated memory and shared memory, and speculative generation of lookahead fetch requests.
상세보기
Gay, Raphael; Olsen, Kirsten, Memory mode categorizations.
상세보기
Greenfield, Zvi, Method and apparatus for communicating between multiple functional units in a computer environment.
상세보기
Scalzi Casper Anthony ; Plambeck Kenneth Ernest, Method of executing perform locked operation instructions for supporting recovery of data consistency if lost due to pro.
상세보기
Greenspan Steven Jay ; Scalzi Casper Anthony ; Plambeck Kenneth Ernest, Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system.
상세보기
Foster Eric M. ; Franklin Dennis E. ; Jackowski Stefan P. ; Wallach David, Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses.
상세보기
Garg, Sanjay; Ghosh, Bipasha; Balram, Nikhil; Sridhar, Kaip; Sahu, Shilpi; Taylor, Richard; Edwards, Gwyn; Tomasi, Loren; Namboodiri, Vipin, Shared memory multi video channel display apparatus and methods.
상세보기
Garg, Sanjay; Ghosh, Bipasha; Balram, Nikhil; Sridhar, Kaip; Sahu, Shilpi; Taylor, Richard; Edwards, Gwyn; Tomasi, Loren; Namboodiri, Vipin, Shared memory multi video channel display apparatus and methods.
상세보기
Garg, Sanjay; Ghosh, Bipasha; Balram, Nikhil; Sridhar, Kaip; Sahu, Shilpi; Taylor, Richard; Edwards, Gwyn; Tomasi, Loren; Namboodiri, Vipin, Shared memory multi video channel display apparatus and methods.
상세보기
Garg, Sanjay; Ghosh, Bipasha; Balram, Nikhil; Sridhar, Kaip; Sahu, Shilpi; Taylor, Richard; Edwards, Gwyn; Tomasi, Loren; Namboodiri, Vipin, Shared memory multi video channel display apparatus and methods.
상세보기
Garg, Sanjay; Ghosh, Bipasha; Balram, Nikhil; Sridhar, Kaip; Sahu, Shilpi; Taylor, Richard; Edwards, Gwyn; Tomasi, Loren; Namboodiri, Vipin, Shared memory multi video channel display apparatus and methods.
상세보기
Garg, Sanjay; Ghosh, Bipasha; Balram, Nikhil; Sridhar, Kaip; Sahu, Shilpi; Taylor, Richard; Edwards, Gwyn; Tomasi, Loren; Namboodiri, Vipin, Shared memory multi video channel display apparatus and methods.
상세보기
Alan Jay Booker ; William Robert Lee ; Neil David Miles, Upgradeable highly integrated embedded CPU system.
상세보기

내보내기 메뉴

내보내기 구분

파일저장
인쇄
메일전송

구성항목

기본정보
상세정보

관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC

저장형식

Text(ASCII format)
Excel format
PIAS분석(.xls)

메일정보

받는사람 (필수): @
보내는사람 (선택): @
제목
내용: KISTI 검색결과 이메일 서비스

안내

총 건의 자료가 검색되었습니다.

다운받으실 자료의 인덱스를 입력하세요. (1-10,000)

검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다.

데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요)

다운로드 파일은 UTF-8 형태로 저장됩니다.
파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오.

Text(ASCII format)
Excel format

AI-Helper ※ AI-Helper는 을 사용합니다.

AI-Helper

안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

연합인증

Multi-processor computer system having dual memory subsytems for enabling concurrent memory access thereto by more than 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

이 특허를 인용한 특허 (18)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Multi-processor computer system having dual memory subsytems for enabling concurrent memory access thereto by more than 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

전체(0) 논문(0) 특허(0) 보고서(0)

이 특허를 인용한 특허 (18)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트