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Three dimensional semiconductor circuit structure with optical interconnection 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-031/0203
  • H01L-027/15
  • H01L-031/12
  • H01L-033/00
출원번호 US-0477785 (1995-06-07)
발명자 / 주소
  • Leedy Glenn J. (Montecito CA)
출원인 / 주소
  • ELM Technology Corporation (Jackson WY 02)
인용정보 피인용 횟수 : 50  인용 특허 : 3

초록

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semicon

대표청구항

An integrated circuit assembly comprising: a plurality of vertically stacked flexible semiconductor membranes each having semiconductor devices and interconnections between the semiconductor devices formed on the membrane; an array of optical transmitter semiconductor devices formed on one of the me

이 특허에 인용된 특허 (3)

  1. Zias Arthur R. (Los Altos CA) Block Barry (Los Altos Hills CA) Mapes Kenneth W. (San Jose CA) Nystrom Norman L. (Sunnyvale CA) Cadwell Robert M. (Los Altos CA), High sensitivity miniature pressure transducer.
  2. Zdeblick Mark (Mountain View CA), Integrated, microminiature electric to fluidic valve.
  3. Jacobsen Stephen C. (Salt Lake City UT) Phillips Richard P. (Salt Lake City UT) Wood John E. (Salt Lake City UT), Systems and methods for sensing position and movement.

이 특허를 인용한 특허 (50)

  1. Leedy, Glenn J, Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer.
  2. Asari,Takuma; Hogan,Daniel, Cell, packaging system, and method for fabricating the packaging system.
  3. Tsunashima Yoshitaka,JPX, Chip for multi-chip semiconductor device and method of manufacturing the same.
  4. Higashida,Takaaki; Okuma,Takafumi; Suetsugu,Daisuke; Nakashima,Seiji; Yamamoto,Kenichi; Nishihara,Munekazu; Sato,Kenichi, Circuit substrate and its manufacturing method.
  5. Woith Blake F. ; Feigenbaum Haim ; Szalay John Steven, Device for testing integrated circuit chips during vibration.
  6. Kaskoun, Kenneth; Gu, Shiqun; Nowak, Matthew M., Devices, systems and methods using through silicon optical interconnects.
  7. Ono, Haruhito; Muraki, Masato, Electrooptic system array, charged-particle beam exposure apparatus using the same, and device manufacturing method.
  8. Ono,Haruhito; Muraki,Masato, Electrooptic system array, charged-particle beam exposure apparatus using the same, and device manufacturing method.
  9. Ono,Haruhito; Muraki,Masato, Electrooptic system array, charged-particle beam exposure apparatus using the same, and device manufacturing method.
  10. Akram, Salman, High density stackable and flexible substrate-based devices and systems and methods of fabricating.
  11. Akram, Salman, High density stackable and flexible substrate-based semiconductor device modules.
  12. Nagase, Toru; Tajima, Minoru; Tokumori, Nobuhiro, IC package, optical transmitter, and optical receiver.
  13. Kanzaki, Masayuki, Infrared ray detector having a vacuum encapsulation structure.
  14. Vogel, Uwe; Amelung, Joerg, Integrated optocoupler with organic light emitter and inorganic photodetector.
  15. Leedy,Glenn J, Lithography device for semiconductor circuit pattern generator.
  16. Cheng, Chin-Hung, Luminescent external dialer for mobile phone.
  17. Leedy,Glenn J, Method of information processing using three dimensional integrated circuits.
  18. Yoshitaka Tsunashima JP, Method of manufacturing a multi-chip semiconductor device effective to improve alignment.
  19. Bruce E. Bernacki ; George T. Krieger ; Fred C. Thomas, III, Optical servo writing.
  20. Wood Alan G. ; Akram Salman ; Farnworth Warren M., Process for manufacturing a semiconductor package with bi-substrate die.
  21. Lang, Dennis, Semiconductor package comprising vertical power transistor.
  22. Wood Alan G. ; Akram Salman ; Farnworth Warren M., Semiconductor package with bi-substrate die.
  23. Leedy, Glenn J., Stacked integrated memory device.
  24. Liu Yung Sheng, Structure and fabrication method for interconnecting light emitting diodes with metallization extending through vias in.
  25. Leedy, Glenn J, Three dimension structure memory.
  26. Leedy, Glenn J, Three dimensional memory structure.
  27. Leedy, Glenn J, Three dimensional memory structure.
  28. Leedy, Glenn J, Three dimensional multi layer memory and control logic integrated circuit structure.
  29. Leedy,Glenn J, Three dimensional structure integrated circuit.
  30. Leedy, Glenn J, Three dimensional structure memory.
  31. Leedy, Glenn J, Three dimensional structure memory.
  32. Leedy, Glenn J, Three dimensional structure memory.
  33. Leedy, Glenn J., Three dimensional structure memory.
  34. Leedy, Glenn J., Three dimensional structure memory.
  35. Leedy, Glenn J., Three dimensional structure memory.
  36. Leedy, Glenn J., Three dimensional structure memory.
  37. Leedy, Glenn J., Three dimensional structure memory.
  38. Leedy, Glenn J., Three dimensional structure memory.
  39. Leedy, Glenn J., Three dimensional structure memory.
  40. Leedy,Glenn J, Three dimensional structure memory.
  41. Leedy,Glenn J., Three dimensional structure memory.
  42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  49. Leedy, Glenn J, Vertical system integration.
  50. Leedy, Glenn J, Vertical system integration.
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