이 특허를 인용한 특허 (73)

1. Bothra Subhas, Air gap dielectric in self-aligned via structures.

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2. Purayath, Vinod R.; Kai, James K.; Pachamuthu, Jayavel; Liang, Jarrett Jun; Matamis, George, Copper interconnects separated by air gaps and method of making thereof.

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3. Stamper Anthony K. ; McGahay Vincent J., Damascene etchback for low .epsilon. dielectric.

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4. H. Jim Fulford, Jr. ; Robert Dawson ; Fred N. Hause ; Basab Bandyopadhyay ; Mark W. Michael ; William S. Brennan, Dielectric having an air gap formed between closely spaced interconnect lines.

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5. Davies, Robert Bruce, Electrical stress protection apparatus and method of manufacture.

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6. Wang John Jianshi ; Fang Hao ; Higashitani Masaaki, Elimination of poly cap easy poly 1 contact for NAND product.

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7. Wang John Jianshi ; Fang Hao ; Higashitani Masaaki, Elimination of poly cap for easy poly1 contact for NAND product.

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8. Kohl,Paul A.; Zhao,Qiang; Bidstrup Allen,Sue Ann, Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections.

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9. Kohl, Paul Albert; Allen, Sue Ann Bidstrup; Henderson, Clifford Lee; Reed, Hollie Anne; Bhusari, Dhananjay M., Fabrication of semiconductor device with air gaps for ultra low capacitance interconnections and methods of making same.

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10. Kohl, Paul Albert; Allen, Sue Ann Bidstrup; Henderson, Clifford Lee; Reed, Hollie Ann; Bhusari, Dhananjay M., Fabrication of semiconductor devices with air gaps for ultra low capacitance interconnections and methods of making same.

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11. Selcuk Asim, Gate structure having polysilicon layer with recessed side portions.

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12. Bergendahl, Marc A.; Demarest, James J.; Penny, Christopher J.; Waskiewicz, Christopher J., Hybrid airgap structure with oxide liner.

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13. Reinberg Alan R., Integrated circuit having a void between adjacent conductive lines.

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14. Gardner Mark I. ; Spikes Thomas E. ; Paiz Robert, Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths.

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15. Lee, Ellis; Hwang, Tsing-Fong, Interconnect structure with an enlarged air gaps disposed between conductive structures or surrounding a conductive structure within the same.

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16. Subramanian Ramkumar ; Lyons Christopher F. ; Okoroanyanwu Uzodinma, Interconnect structure with low k dielectric materials and method of making the same with single and dual damascene techniques.

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17. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Interlevel dielectric with air gaps to lessen capacitive coupling.

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18. Lee Yu-Hua,TWX ; Wu Cheng-Ming,TWX, Keyhole-free process for high aspect ratio gap filing.

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19. Jang Syun-Ming,TWX, Low dielectric constant intermetal dielectric (IMD) by formation of air gap between metal lines.

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20. Cox William P., Low dielectric constant material and method of application to isolate conductive lines.

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21. Gaw Eng T. ; Vu Quat T. ; Fraser David B. ; Chiang Chien ; Young Ian A. ; Marieb Thomas N. D., Method and structure for reducing interconnect system capacitance through enclosed voids in a dielectric layer.

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22. Ping Liou TW, Method for fabricating high-Q inductance device in monolithic technology.

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23. Ping Liou TW, Method for fabricating high-Q inductance device in monolithic technology.

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24. De Santi Giorgio,ITX ; Zanotti Luca,ITX ; Crisenza Giuseppe,ITX, Method for final passivation of integrated circuit.

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25. Kitch Vassili Victor, Method for formation of an air gap in an integrated circuit architecture.

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26. Singh Abha R. ; Balasinski Artur P. ; Li Ming M., Method for forming controlled voids in interlevel dielectric.

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27. Yu, Hung-Chih; Chen, Chien-Mao, Method for forming semiconductor structure.

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28. Boeck Bruce Allen ; Wetzel Jeff Thomas ; Sparks Terry Grant, Method for manufacturing a low dielectric constant inter-level integrated circuit structure.

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29. Lin Shih-Chi,TWX ; Chen Yen-Ming,TWX, Method for manufacturing arch air gap in multilevel interconnection.

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30. Yew Tri-Rung,TWX ; Lur Water,TWX ; Chung Hsien-Ta,TWX, Method for manufacturing dielectric layer.

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31. Chen, Tsu-Chiang; Liao, Yu-Mei; Chen, Cheng-Kuen, Method for manufacturing semiconductor device.

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32. Kim Chang-gyu,KRX ; Choi Ji-hyun,KRX ; Hong Seok-ji,KRX, Method for planarizing a semiconductor substrate.

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33. Subhas Bothra ; Rao Annapragada, Method for reducing the capacitance between interconnects by forming voids in dielectric material.

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34. Charles E. May, Method of coupling capacitance reduction.

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35. Hong Gary,TWX, Method of fabricating conductive line structure.

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36. Lee Shih-Ked ; Yen Chu-Tsao ; Hsueh Cheng-Chen Calvin,TWX ; Shih James R. ; Lien Chuen-Der, Method of forming air gaps for reducing interconnect capacitance.

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37. Broekaart, Marcel Eduard Irene; Guelen, Josephus Franciscus Antonius Maria; Gerritsen, Eric, Method of forming an etch stop layer in a semiconductor device.

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38. Joaquim Torres FR; Philippe Gayet FR; Michel Haond FR, Method of forming insulated metal interconnections in integrated circuits.

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39. Yang, Ming-Sheng; Liu, Chih-Chien, Method of forming interconnect structure with low dielectric constant.

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40. Matsumoto Akira,JPX, Method of making a semiconductor device.

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41. Yasushi Miyamoto JP, Method of manufacturing a semiconductor device with air gaps formed between metal leads.

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42. Lin Shih-Chi,TWX ; Chen Yen-Ming,TWX ; Chang Juin-Jie,TWX ; Huang Kuei-Wu,TWX, Method of manufacturing air gap in multilevel interconnection.

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43. Shih-Chi Lin TW; Yen-Ming Chen TW; Juin-Jie Chang TW; Kuei-Wu Huang TW, Method of manufacturing air gap in multilevel interconnection.

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44. Yang Fu-Liang,TWX ; Chang Tony,TWX, Method of manufacturing intermetal dielectrics for sub-half-micron semiconductor devices.

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45. Bang David, Method of producing air gap for reducing intralayer capacitance in metal layers in damascene metalization process and product resulting therefrom.

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46. Lai Wei-Sheng,TWX ; Chang Yu-Ching,TWX ; Ge Chun-Hu,TWX ; Chen Chih-Ming,TWX, Method to provide low dielectric constant voids between adjacent conducting lines in a semiconductor device.

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47. Tang, Sanh; Zhang, Ming, Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry.

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48. Morinaga Shirou,JPX, Methods of manufacturing a semiconductor device with pores formed between and over wiring patterns of an interlevel insulating layer.

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49. Jin Yang Kim KR; Si-Woo Lee KR; Won Seong Lee KR; Sang-Pil Sim KR, Multilayer passivation process for forming air gaps within a dielectric between interconnections.

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50. Davies, Robert Bruce, Power semiconductor device and method therefor.

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51. Papasouliotis, George D.; Tas, Robert D.; Van Cleemput, Patrick A.; van Schravendijk, Bart, Process for depositing F-doped silica glass in high aspect ratio structures.

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52. Cronin John Edward ; Stamper Anthony Kendall, Process of making a microcavity structure and applications thereof.

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53. Davies, Robert Bruce, Radio frequency power semiconductor device comprising matrix of cavities as dielectric isolation structure.

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54. Hamid Partovi ; Chun Jiang ; Bill Yowjuang Liu, Selective air gap insulation.

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55. Aoyama, Junichi; Kobayashi, Toshio, Semiconductor device and wiring forming method in semiconductor device.

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56. Aoyama,Junichi; Kobayashi,Toshio, Semiconductor device and wiring forming method in semiconductor device.

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57. Grivna, Gordon M., Semiconductor device having regions of low substrate capacitance.

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58. Purayath, Vinod R.; Kai, James K.; Pachamuthu, Jayavel; Liang, Jarrett Jun; Matamis, George, Semiconductor device with copper interconnects separated by air gaps.

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59. Bang David, Semiconductor interconnect structure with air gap for reducing intralayer capacitance in metal layers in damascene meta.

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60. Brennan William S. ; Dawson Robert ; Fulford ; Jr. H. Jim ; Hause Fred N. ; Bandyopadhyay Basab ; Michael Mark W., Semiconductor interlevel dielectric having a polymide for producing air gaps.

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61. Liu, Wei-Hsin; Tsai, Bin-Siang, Semiconductor process.

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62. Tischler, Michael Albert, Semiconductor structure and method of manufacture.

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63. Liu, Wei-Hsin; Tsai, Bin-Siang, Semiconductor structure and process thereof.

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64. Miyamoto Yasushi,JPX, Semiconductor structure with air gaps formed between metal leads.

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65. Cronin, John Edward; Stamper, Anthony Kendall, Specially shaped contact via and integrated circuit therewith.

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66. Cronin, John Edward; Stamper, Anthony Kendall, Specially shaped contact via and integrated circuit therewith.

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67. Smith, Gregory C., Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device.

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68. Huang, Chien-Hua; Yao, Hsin-Chieh; Lee, Chung-Ju, Tapered sidewall conductive lines and formation thereof.

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69. Morey, Ian J.; Ellingboe, Susan; Flanner, Janet M.; Janowiak, Christine M.; Lang, John, Technique for etching a low capacitance dielectric layer.

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70. Moslehi Mehrdad M., Ultra high-speed chip interconnect using free-space dielectrics.

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71. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

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72. Patrick A. Van Cleemput ; George D. Papasouliotis ; Mark A. Logan ; Bart van Schravendijk ; William J. King, Very high aspect ratio gapfill using HDP.

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73. Jang Syun-Ming,TWX, Void forming method for fabricating low dielectric constant dielectric layer.

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