이 특허를 인용한 특허 (304)

1. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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2. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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3. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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4. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.

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11. Heidari-Bateni, Ghobad; Plunkett, Robert Thomas, Adaptive, multimode rake receiver for dynamic search and multipath reception.

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12. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.

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13. Mar, Monte, Apparatus and method for programmable power management in a programmable analog circuit block.

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14. Pedersen, Bruce B.; Rahim, Irfan, Apparatus for improving reliability of electronic circuitry and associated methods.

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15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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18. Master,Paul L.; Smith,Stephen J.; Watson,John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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19. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.

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20. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.

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21. Hogenauer, Eugene B., Arithmetic node including general digital signal processing functions for an adaptive computing machine.

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22. Howard, Ric; Katragadda, Ramana V., Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture.

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23. de Waal, Abraham B.; Diard, Franck R., Automatic quality testing of multimedia rendering by software drivers.

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24. Sullam, Bert; Kutz, Harold; Mar, Monte; Thiagaragen, Eashwar; Williams, Timothy; Wright, David G., Autonomous control in a programmable system.

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25. Redgrave, Jason; Schmit, Herman, Barrel shifter implemented on a configurable integrated circuit.

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26. Roe, Steve; Nemecek, Craig, Breakpoint control in an in-circuit emulation system.

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27. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.

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28. Kengo Azegami JP; Koichi Yamashita JP, Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time.

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29. Vorbach, Martin, Chip including memory element storing higher level memory data on a page by page basis.

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30. Wright, David G.; Williams, Timothy J., Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes.

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31. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.

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32. Schmit,Herman; Redgrave,Jason, Clock distribution in a configurable IC.

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33. Schmit,Herman; Redgrave,Jason, Clock distribution in a configurable IC.

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34. Synder, Warren; Sullam, Bert, Clock driven dynamic datapath chaining.

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35. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.

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36. Rohe,Andre; Teig,Steven, Concurrent optimization of physical design and operational cycle assignment.

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37. Nemecek, Craig, Conditional branching in an in-circuit emulation system.

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38. Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.

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39. Teig, Steven, Configurable IC having a routing fabric with storage elements.

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40. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.

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41. Teig, Steven; Schmit, Herman; Redgrave, Jason, Configurable IC having a routing fabric with storage elements.

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42. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configurable routing resources that have asymmetric input and/or outputs.

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43. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configuration logic resources that have asymmetric inputs and/or outputs.

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44. Teig, Steven; Redgrave, Jason, Configurable IC with error detection and correction circuitry.

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45. Teig, Steven; Schmit, Herman; Redgrave, Jason; Chandra, Vikas, Configurable IC with interconnect circuits that also perform storage operations.

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46. Teig,Steven; Schmit,Herman; Redgrave,Jason; Chandra,Vikas, Configurable IC with interconnect circuits that also perform storage operations.

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47. Hutchings,Brad; Schmit,Herman; Teig,Steven, Configurable IC with interconnect circuits that have select lines driven by user signals.

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48. Schmit, Herman; Redgrave, Jason, Configurable IC with large carry chains.

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49. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu, Configurable IC with logic resources with offset connections.

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50. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu, Configurable IC with routing circuits with offset connections.

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51. Schmit,Herman; Teig,Steven; Hutchings,Brad; Huang,Randy Renfu, Configurable IC with routing circuits with offset connections.

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52. Redgrave, Jason; Schmit, Herman; Teig, Steven; Hutchings, Brad L.; Huang, Randy R., Configurable IC'S with large carry chains.

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53. Schmit,Herman; Teig,Steven; Hutchings,Brad; Huang,Randy Renfu; Redgrave,Jason, Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs.

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54. Teig, Steven; Redgrave, Jason, Configurable IC's with dual carry chains.

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55. Schmit,Herman; Teig,Steven; Hutchings,Brad; Huang,Randy Renfu, Configurable IC's with logic resources with offset connections.

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56. Teig, Steven; Caldwell, Andrew; Redgrave, Jason, Configurable ICs that conditionally transition through configuration data sets.

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57. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Configurable circuits, IC's and systems.

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58. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Configurable circuits, IC's, and systems.

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59. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Configurable circuits, IC's, and systems.

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60. Schmit,Herman; Butts,Michael; Hutchings,Brad L.; Teig,Steven, Configurable circuits, IC's, and systems.

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61. Schmit,Herman; Butts,Michael; Hutchings,Brad L.; Teig,Steven, Configurable circuits, IC's, and systems.

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62. Schmit,Herman; Butts,Michael; Hutchings,Brad L.; Teig,Steven, Configurable circuits, IC's, and systems.

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63. Schmit,Herman; Butts,Michael; Hutchings,Brad L.; Teig,Steven, Configurable circuits, IC's, and systems.

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64. Schmit,Herman; Butts,Michael; Hutchings,Brad L.; Teig,Steven, Configurable circuits, IC's, and systems.

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65. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.

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66. Schmit, Herman; Caldwell, Andrew; Teig, Steven, Configurable integrated circuit with a 4-to-1 multiplexer.

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67. Rohe, Andre; Teig, Steven, Configurable integrated circuit with built-in turns.

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68. Rohe, Andre; Teig, Steven, Configurable integrated circuit with built-in turns.

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69. Rohe,Andre; Teig,Steven, Configurable integrated circuit with built-in turns.

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70. Rohe, Andre; Teig, Steven, Configurable integrated circuit with different connection schemes.

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71. Rohe,Andre; Teig,Steven, Configurable integrated circuit with different connection schemes.

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72. Teig, Steven; Redgrave, Jason; Horel, Timothy, Configurable integrated circuit with error correcting circuitry.

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73. Rohe,Andre; Teig,Steven, Configurable integrated circuit with offset connection.

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74. Rohe,Andre; Teig,Steven, Configurable integrated circuit with offset connections.

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75. Schmit,Herman; Teig,Steven; Hutchings,Brad, Configurable integrated circuit with parallel non-neighboring offset connections.

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76. Schmit,Herman; Teig,Steven, Configurable logic circuits with commutative properties.

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77. Schmit,Herman; Teig,Steven, Configurable logic circuits with commutative properties.

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78. Vorbach, Martin; Nuckel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.

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79. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.

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80. Voogel, Martin; Teig, Steven; Chanack, Thomas S.; Caldwell, Andrew; Ko, Jung; Chandler, Trevis, Configurable storage elements.

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81. Voogel, Martin; Teig, Steven; Chanack, Thomas S.; Caldwell, Andrew; Ko, Jung; Chandler, Trevis, Configurable storage elements.

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82. Chandler, Trevis; Redgrave, Jason; Voogel, Martin, Configuration context switcher.

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83. Chandler, Trevis; Redgrave, Jason; Voogel, Martin, Configuration context switcher.

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84. Chandler, Trevis; Entjer, Joe; Voogel, Martin; Redgrave, Jason, Configuration context switcher with a clocked storage element.

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85. Chandler, Trevis; Entjer, Joe; Voogel, Martin; Redgrave, Jason, Configuration context switcher with a clocked storage element.

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86. Voogel, Martin; Redgrave, Jason; Chandler, Trevis, Configuration context switcher with a latch.

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87. Rangasayee Krishna, Configuration eprom with programmable logic.

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88. Best, Andrew; Ogami, Kenneth; Zhaksilikov, Marat, Configuration of programmable IC design elements.

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89. Rubin, Owen Robert; Murray, Eric; Uhrig, Nalini Praba, Consumer product distribution in the embedded system market.

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90. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.

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91. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.

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92. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.

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93. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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94. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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95. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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96. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

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97. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

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98. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing system having integrated pipelined array data processor.

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99. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.

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100. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.

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101. Synder, Warren; Sullam, Bert, Dynamically configurable and re-configurable data path.

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102. Martel Sylvain ; Lafontaine Serge R. ; Hunter Ian W., Dynamically reconfigurable hardware system for real-time control of processes.

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103. Schmit, Herman; Redgrave, Jason, Embedding memory between tile arrangement of a configurable IC.

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104. Schmit,Herman; Redgrave,Jason, Embedding memory between tile arrangement of a configurable IC.

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105. Schmit,Herman; Redgrave,Jason, Embedding memory within tile arrangement of a configurable IC.

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106. Schmit, Herman; Redgrave, Jason, Embedding memory within tile arrangement of an integrated circuit.

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107. Beal Samuel W. ; Kaptonoglu Sinan ; Lien Jung-Cheun ; Shu William ; Chan King W. ; Plants William C., Enhanced field programmable gate array.

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108. Nemecek, Craig; Roe, Steve, External interface for event architecture.

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109. Furtek, Frederick Curtis; Master, Paul L., External memory controller.

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110. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.

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111. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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112. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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113. New Bernard J., Field programmable gate array with dedicated computer bus interface and method for configuring both.

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114. McGowan John E., Field programmable gate array with mask programmed analog function circuits.

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115. John E. McGowan, Field programmable gate array with mask programmed input and output buffers.

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116. McGowan John E., Field programmable gate array with mask programmed input and output buffers.

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117. Pleis, Matthew A.; Ogami, Kenneth Y.; Zhaksilikov, Marat, Graphical user interface for dynamically reconfiguring a programmable device.

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118. Anderson, Doug, Graphical user interface with user-selectable list-box.

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119. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.

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120. Scheuermann,Walter James, Hardware implementation of the secure hash standard.

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121. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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122. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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123. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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124. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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125. Master,Paul L.; Hogenauer,Eugene; Scheuermann,Walter James, Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements.

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126. Chatter Mukesh, High performance self modifying on-the-fly alterable logic FPGA, architecture and method.

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127. Hutchings, Brad; Schmit, Herman; Teig, Steven, Hybrid configurable circuit for a configurable IC.

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128. Hutchings,Brad; Schmit,Herman; Teig,Steven, Hybrid configurable circuit for a configurable IC.

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129. Hutchings,Brad; Schmit,Herman; Redgrave,Jason, Hybrid logic/interconnect circuit in a configurable IC.

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130. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

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131. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

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132. Pugh, Daniel J.; Caldwell, Andrew, IC that efficiently replicates a function to save logic and routing resources.

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133. Nemecek, Craig; Roe, Steve, In-circuit emulator and pod synchronized boot.

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134. Furtek, Frederick Curtis; Master, Paul L.; Plunkett, Robert Thomas, Input/output controller node in an adaptable computing environment.

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135. Seguine, Dennis R., Input/output multiplexer bus.

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136. Sequine, Dennis R., Input/output multiplexer bus.

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137. Heidari-Bateni, Ghobad; Sambhwani, Sharad D., Internal synchronization control for adaptive integrated circuitry.

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138. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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139. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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140. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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141. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.

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142. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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143. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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144. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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145. Redgrave, Jason; Schmit, Herman, Method and apparatus for accessing contents of memory cells.

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146. Redgrave, Jason, Method and apparatus for accessing stored data in a reconfigurable IC.

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147. Redgrave,Jason, Method and apparatus for accessing stored data in a reconfigurable IC.

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148. Caldwell, Andrew; Schmit, Herman; Teig, Steven, Method and apparatus for decomposing functions in a configurable IC.

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149. Caldwell, Andrew; Schmit, Herman; Teig, Steven, Method and apparatus for decomposing functions in a configurable IC.

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150. Burke, David, Method and apparatus for executing standard functions in a computer system using a field programmable gate array.

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151. Caldwell, Andrew; Teig, Steven, Method and apparatus for function decomposition.

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152. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.

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153. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.

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154. Rohe,Andre; Teig,Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.

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155. Redgrave, Jason; Caldwell, Andrew; Teig, Steven, Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC.

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156. Redgrave, Jason; Hutchings, Brad; Schmit, Herman; Teig, Steven, Method and apparatus for performing shifting in an integrated circuit.

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157. Pugh, Daniel J., Method and apparatus for performing two's complement multiplication.

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158. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

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159. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

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160. Master, Paul L., Method and system for achieving individualized protected space in an operating system.

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161. Master, Paul L., Method and system for creating and programming an adaptive computing engine.

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162. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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163. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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164. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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165. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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166. Boehm, Janko; Elfering, Herwig Gustav; Hess, Thomas; Metz, Daniel, Method and system for personalized I/O device initialization.

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167. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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168. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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169. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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170. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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171. Master, Paul L.; Scheuermann, W. James, Method and system for reducing the time-to-market concerns for embedded system design.

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172. Vorbach, Martin, Method for debugging reconfigurable architectures.

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173. Vorbach, Martin, Method for debugging reconfigurable architectures.

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174. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.

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175. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.

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176. Perrin, Jon; Seguine, Dennis, Method for parameterizing a user module.

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177. Vorbach, Martin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.

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178. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.

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179. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.

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180. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits.

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181. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Method of processing data with an array of data processors according to application ID.

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182. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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183. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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184. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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185. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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186. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.

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187. Ebeling, W. H. Carl; Hogenauer, Eugene B., Method, system and software for programming reconfigurable hardware.

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188. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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189. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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190. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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191. Vorbach, Martin, Methods and devices for treating and/or processing data.

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192. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.

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193. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.

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194. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.

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195. Snyder, Warren, Microcontroller programmable system on a chip with programmable interconnect.

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196. Snyder, Warren S, Microcontroller programmable system on a chip with programmable interconnect.

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197. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Multi-processor bus and cache interconnection system.

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198. Vorbach, Martin, Multi-processor with selectively interconnected memory units.

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199. Vorbach, Martin, Multiprocessor having associated RAM units.

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200. Vorbach, Martin; Baumgarte, Volker, Multiprocessor having runtime adjustable clock and clock dependent power supply.

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201. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Non-sequentially configurable IC.

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202. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Non-sequentially configurable IC.

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203. Schmit,Herman; Butts,Michael; Hutchings,Brad L.; Teig,Steven, Non-sequentially configurable IC.

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204. Kutz, Harold, Numerical band gap.

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205. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.

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206. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.

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207. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.

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208. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.

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209. Rohe,Andre; Teig,Steven, Operational cycle assignment in a configurable IC.

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210. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.

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211. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.

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212. Rohe,Andre; Teig,Steven; Schmit,Herman; Redgrave,Jason; Caldwell,Andrew, Operational time extension.

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213. Snyder, Warren S.; Mar, Monte, PSOC architecture.

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214. Snyder, Warren; Mar, Monte, PSOC architecture.

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215. Snyder, Warren S.; Mar, Monte, PSoC architecture.

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216. Snyder, Warren S.; Mar, Monte, PSoC architecture.

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217. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.

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218. Patel Rakesh H. ; Norman Kevin A., Partially reconfigurable programmable logic device.

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219. Pugh, Daniel J.; Redgrave, Jason; Caldwell, Andrew, Performing mathematical and logical operations in multiple sub-cycles.

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220. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

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221. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

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222. Ogami, Kenneth Y., Power management architecture, method and configuration system.

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223. Ogami, Kenneth Y., Power management architecture, method and configuration system.

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224. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).

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225. Scheuermann,W. James, Processing architecture for a reconfigurable arithmetic node.

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226. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.

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227. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.

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228. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.

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229. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.

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230. Gamal Abbas El ; El-Avat Khaled A. ; Mohsen Amr, Programmable interconnect architecture.

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231. Beat, Robert Charles, Programmable logic fabric.

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232. Snyder, Warren, Programmable microcontroller architecture.

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233. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture(mixed analog/digital).

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234. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture(mixed analog/digital).

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235. Thiagarajan, Eashwar; Sivadasan, Mohandas Palatholmana; Rohilla, Gajender; Kutz, Harold; Mar, Monte, Programmable sigma-delta analog-to-digital converter.

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236. Snyder, Warren; Maheshwari, Dinesh; Ogami, Kenneth; Hastings, Mark, Providing hardware independence to automate code generation of processing device firmware.

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237. Voogel, Martin; Redgrave, Jason; Chandler, Trevis, Reading configuration data from internal storage node of configuration storage circuit.

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238. Teig, Steven; Schmit, Herman; Redgrave, Jason, Reconfigurable IC that has sections running at different looperness.

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239. Teig,Steven; Schmit,Herman; Redgrave,Jason, Reconfigurable IC that has sections running at different looperness.

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240. Teig, Steven; Schmit, Herman; Redgrave, Jason, Reconfigurable IC that has sections running at different reconfiguration rates.

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241. Teig, Steven; Schmit, Herman; Redgrave, Jason, Reconfigurable IC that has sections running at different reconfiguration rates.

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242. Teig,Steven; Schmit,Herman; Redgrave,Jason, Reconfigurable IC that has sections running at different reconfiguration rates.

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243. Rupp Charle R., Reconfigurable computer architecture for use in signal processing applications.

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244. Vorbach, Martin, Reconfigurable elements.

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245. Vorbach, Martin, Reconfigurable elements.

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246. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.

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247. Vorbach, Martin, Reconfigurable sequencer structure.

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248. Vorbach, Martin, Reconfigurable sequencer structure.

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249. Vorbach, Martin, Reconfigurable sequencer structure.

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250. Vorbach, Martin, Reconfigurable sequencer structure.

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251. Pleis, Matthew A.; Sullam, Bert; Lesher, Todd, Reconfigurable testing system and method.

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252. Pleis,Matthew A.; Sullam,Bert; Lesher,Todd, Reconfigurable testing system and method.

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253. Caldwell,Andrew; Redgrave,Jason, Replacing circuit design elements with their equivalents.

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254. Vorbach, Martin; Bretz, Daniel, Router.

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255. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.

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256. Master, Paul L.; Murray, Eric; Mehegan, Joseph; Plunkett, Robert Thomas, Secure storage of program code for an embedded system.

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257. Fukutome, Takahiro, Semiconductor device.

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258. Caldwell, Andrew; Teig, Steven, Sequential delay analysis by placement engines.

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259. Nemecek, Craig, Sleep and stall in an in-circuit emulation system.

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260. Wicker, Jr., David J., State machine in a programmable logic device.

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261. Master,Paul L.; Watson,John, Storage and delivery of device features.

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262. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.

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263. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.

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264. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.

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265. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.

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266. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.

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267. Redgrave,Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.

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268. Redgrave,Jason; Hutchings,Brad; Schmit,Herman; Teig,Steven, Sub-cycle configurable hybrid logic/interconnect circuit.

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269. Ogami, Kenneth; Best, Andrew; Zhaksilikov, Marat, System and method for controlling a target device.

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270. Anderson, Douglas H.; Ogami, Kenneth Y., System and method for dynamically generating a configuration datasheet.

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271. Ogami, Kenneth Y.; Hood, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.

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272. Ogami, Kenneth Y.; Hood, III, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.

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273. Schmit, Herman; Caldwell, Andrew; Hutchings, Brad; Redgrave, Jason; Teig, Steven, System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture.

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274. Schmit, Herman; Caldwell, Andrew; Hutchings, Brad; Redgrave, Jason; Teig, Steven, System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture.

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275. Schmit, Herman; Teig, Steven; Hutchings, Brad, System and method for providing more logical memory ports than physical memory ports.

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276. Schmit, Herman; Teig, Steven; Hutchings, Brad, System and method for providing more logical memory ports than physical memory ports.

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277. Huang, Randy R.; Voogel, Martin; Hu, Jingcao; Teig, Steven, System and method for reducing reconfiguration power.

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278. Pleis, Matthew A.; Ogami, Kenneth Y.; Snyder, Warren, System and method of dynamically reconfiguring a programmable integrated circuit.

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279. Schmit, Herman; Pugh, Daniel J.; Teig, Steven, System and method of mapping memory blocks in a configurable integrated circuit.

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280. Schmit, Herman; Pugh, Daniel J.; Teig, Steven, System and method of providing a memory hierarchy.

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281. Jacob,Rojit; Chuang,Dan Minglun, System and method using embedded microprocessor as a node in an adaptable computing machine.

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282. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.

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283. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.

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284. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.

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285. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.

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286. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.

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287. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, III, Frederick Redding, Techniques for generating microcontroller configuration information.

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288. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, Rick, Techniques for generating microcontroller configuration information.

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289. Venkataraman, Garthik; Kutz, Harold; Mar, Monte, Temperature sensor with digital bandgap.

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290. Teig, Steven; Caldwell, Andrew, Timing operations in an IC with configurable circuits.

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291. Snyder, Warren; Sullam, Bert; Mohammed, Haneef, Universal digital block interconnection and channel routing.

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292. Pugh, Daniel J.; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Use of hybrid interconnect/logic circuits for multiplication.

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293. Bartz, Manfred; Zhaksilikov, Marat; Anderson, Doug, User interface for efficiently browsing an electronic document using data-driven tabs.

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294. Redgrave, Jason, User registers implemented with routing circuits in a configurable IC.

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295. Redgrave, Jason, User registers implemented with routing circuits in a configurable IC.

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296. Redgrave, Jason, Users registers implemented with routing circuits in a configurable IC.

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297. Schmit,Herman; Redgrave,Jason, Users registers in a reconfigurable IC.

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298. Schmit, Herman; Teig, Steven, VPA interconnect circuit.

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299. Schmit,Herman; Teig,Steven, VPA interconnect circuit.

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300. Schmit,Herman; Teig,Steven, VPA logic circuits.

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301. Schmit,Herman; Teig,Steven, VPA logic circuits.

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302. Hutchings, Brad, Variable width management for a memory of a configurable IC.

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303. Hutchings, Brad, Variable width writing to a memory of an IC.

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304. Sivadasan, Mohandas Palatholmana; Rohilla, Gajendar, Voltage controlled oscillator delay cell and method.

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