이 특허를 인용한 특허 (59)

1. Puzella, Angelo M.; Dupuis, Patricia S.; Lemmler, Craig C.; Bozza, Donald A.; Bellahrossi, Kassam K.; Robbins, James A.; Francis, John B., Active electronically scanned array (AESA) card.

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2. Dibene, II, Joseph T.; Hartke, David H.; Derian, Edward J.; Hoge, Carl E.; Broder, James M.; San Andres, Jose B.; Riel, Joseph S., Apparatus for delivering power to high performance electronic assemblies.

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3. Joseph Ted Dibene, II ; David H. Hartke ; James Hjerpe Kaskade ; Carl E. Hoge, Apparatus for providing power to a microprocessor with integrated thermal and EMI management.

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4. Weber Bernd,DEX ; Hofsaess Dietmar,DEX ; Butschkau Werner,DEX ; Dittrich Thomas,DEX ; Schiefer Peter,DEX, Arrangement including a substrate for power components and a heat sink, and a method for manufacturing the arrangement.

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5. Paquette, Jeffrey; Cheyne, Scott R.; Ellsworth, Joseph R., Assembly to provide thermal cooling.

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6. Boyce, Martin J., Circuit board assembly for welding power supply.

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7. Ian P. Shaeffer ; Everett Basham, Connection block for interfacing a plurality of printed circuit boards.

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8. Danello, Paul A.; Cheyne, Scott R.; Ellsworth, Joseph R.; Tellinghuisen, Thomas J., Cooling active circuits.

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9. Cheyne, Scott R.; Paquette, Jeffrey; Ackerman, Mark, Cooling of coplanar active circuits.

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10. Tissot, Serge; Demonchaux, Thierry; Oconte, Philippe; Vanneuville, Guy, Device for cooling an electronic card by conduction comprising heat pipes, and corresponding method of fabrication.

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11. Hamilton Roger Duane ; Kang Sukhvinder Singh, Dual heat sink assembly for cooling multiple electronic modules.

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12. Martin, Gerard-Marie, Electronic assembly comprising a sole plate forming a heat sink.

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13. Mandel, Larry M, Electronic assembly for removing heat from a flip chip.

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14. Wakana, Yoshinori; Igarashi, Takeshi; Kameshiro, Yasuro; Hattori, Takashi; Kamoshida, Masaru, Electronic control device.

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15. Oota, Shinsuke; Saitou, Mitsuhiro; Oohashi, Yutaka, Electronic control unit and method of manufacturing the same.

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16. Herbert, Edward, Flexible heat sinks and method of attaching flexible heat sinks.

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17. Tseng, Chun Fa; Yang, Chi Hsueh; Huang, Yu Nien, Heat dissipation module.

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18. Butterbaugh Matthew Allen ; Hamilton Roger Duane ; Kang Sukhvinder Singh, Heat sink assembly for cooling electronic modules.

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19. Paquette, Jeffrey; Cheyne, Scott R.; Ellsworth, Joseph R.; Martinez, Michael P.; Trahan, Michael R., Heat sink interface having three-dimensional tolerance compensation.

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20. Tobin Thomas M. ; Schultheis Gary Robert, Heat sink structure for fast network hubs.

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21. Yoshizumi, Takahisa; Hoshiyama, Naoto, Heat-transfer plate, heat-transfer plate module, and submarine apparatus.

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22. Hartke, David H.; DiBene, II, Joseph Ted, Integrated power delivery with flex circuit interconnection for high density power circuits for integrated circuits and systems.

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23. Dibene ; II Joseph Ted ; Hartke David, Inter-circuit encapsulated packaging.

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24. Joseph Ted DiBene, II ; David Hartke, Inter-circuit encapsulated packaging for power delivery.

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25. Lynch, Fernando; Steedly, James; Bremser, Michael; Kohan, Kamran; Kean, Johnny, LED-based light engine having thermally insulated zones.

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26. Hashemi Hassan S., Leadless chip carrier design and structure.

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27. Hashemi, Hassan S., Leadless chip carrier design and structure.

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28. Megahed, Mohamed; Hashemi, Hassan S., Leadless chip carrier with embedded inductor.

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29. Hashemi, Hassan S., Leadless flip chip carrier design and structure.

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30. DiBene, II, Joseph Ted; Hartke, David H., Method and apparatus for providing power to a microprocessor with integrated thermal and EMI management.

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31. DiBene, II,Joseph T.; Hartke,David H.; Kaskade,James J. Hjerpe; Hoge,Carl E., Method and apparatus for providing power to a microprocessor with integrated thermal and EMI management.

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32. Roman M. Katchmar CA, Method and device for heat dissipation in an electronics system.

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33. DiBene, II,Joseph T.; Derian,Edward J., Micro-spring interconnect systems for low impedance high power applications.

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34. Ellsworth, Joseph R.; Martinez, Michael P.; McCordic, Craig H.; Paquette, Jeffrey; Cheyne, Scott R., Modular architecture for scalable phased array radars.

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35. Ellsworth, Joseph R.; Martinez, Michael P.; McCordic, Craig H.; Paquette, Jeffrey; Cheyne, Scott R., Modular architecture for scalable phased array radars.

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36. Yamanaka, Yasunori, Mounting structure for power module, and motor controller including the same.

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37. Kenji Koya JP, Multilayer printed wiring board provided with injection hole for thermally conductive filler.

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38. Puzella, Angelo M; Licciardello, Joseph A.; Dupuis, Patricia S.; Francis, John B.; Komisarek, Kenneth S.; Bozza, Donald A.; Alm, Roberto W., Panel array.

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39. Katchmar Roman,CAX, Printed circuit board and heat sink arrangement.

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40. Butterbaugh Matthew Allen ; Hamilton Roger Duane ; Kang Sukhvinder Singh, Push pin assembly for heat sink for cooling electronic modules.

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41. Puzella, Angelo M.; Crowder, Joseph M.; Dupuis, Patricia S.; Fallica, Michael C.; Francis, John B.; Licciardello, Joseph A., Radio frequency interconnect circuits and techniques.

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42. Strickland, Peter Charles; Borysenko, Sergiy; Jessup, Bradley, Reduced thermal transfer to Peltier cooled FETs.

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43. Strickland, Peter Charles; Borysenko, Sergiy; Jessup, Bradley, Reduced thermal transfer to Peltier cooled FETs.

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44. Hartke, David H.; DiBene, II, J. Ted, Right-angle power interconnect electronic packaging assembly.

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45. Sato, Takato; Onishi, Yukio; Kono, Hiroyuki; Yoshizawa, Hiroaki; Watari, Toshio; Yamasaki, Hiromi, Semiconductor device.

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46. Derian, Edward J.; DiBene, II, Joseph Ted; Hartke, David H., Separable power delivery connector.

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47. Hashemi, Hassan S.; Cote, Kevin, Structure and method for fabrication of a leadless chip carrier.

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48. Coccioli, Roberto; Megahed, Mohamed; Hashemi, Hassan S., Structure and method for fabrication of a leadless chip carrier with embedded antenna.

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49. Hashemi, Hassan S.; Cote, Kevin J., Structure and method for fabrication of a leadless multi-die carrier.

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50. Ma, Qing; Maveety, Jim; Tran, Quan, Structure for reducing die corner and edge stresses in microelectronic packages.

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51. Dibene, II, Joseph Ted; Hartke, David H.; Hoge, Carl E.; Derian, Edward J., System and method for processor power delivery and thermal management.

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52. Brandon, Mark A.; Canfield, Shawn; Edwards, David L.; Genest, Robert R.; Kemink, Randall G.; Mullady, Robert K.; Torok, John G., System to improve an in-line memory module.

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53. Brandon, Mark A.; Canfield, Shawn; Edwards, David L.; Genest, Robert R.; Kemink, Randall G.; Mullady, Robert K.; Torok, John G., System to improve an in-line memory module.

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54. DeVeau George Frank ; Li Daren, Thermal housing for optical circuits.

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55. Wu, Chun-Ming; Yu, Ming-Han, Thermal module structure.

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56. Paquette, Jeffrey; Cheyne, Scott R., Translating hinge.

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57. Paquette, Jeffrey; Cheyne, Scott R., Translating hinge.

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58. Puzella, Angelo M.; Bozza, Donald A.; Robbins, James A.; Francis, John B., Transmit/receive daughter card with integral circulator.

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59. Dibene, II, Joseph Ted; Hartke, David H.; Hoge, Carl E.; Derian, Edward J., Ultra-low impedance power interconnection system for electronic packages.

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