초록 ▼

The data encryption system includes a first stage and a second stage data encryption engine in combination with a micro control system. The data encryption system is responsive to control signals from the micro control system. The first stage is comprised of an 8-bit bus input and output from the fi

The data encryption system includes a first stage and a second stage data encryption engine in combination with a micro control system. The data encryption system is responsive to control signals from the micro control system. The first stage is comprised of an 8-bit bus input and output from the first stage to the second stage data encryption engine of 64-bits. The input bus of the first stage is gated to a plurality of 8-bit registers through a plurality of AND gates having a respective one of the AND gate inputs in communication with the 8-bit bus and output from the respective AND gate directed to a respective input of the respective 8-bit registers for selectively gating data from the 8-bit bus to respective ones of the 8-bit registers. A demultiplexer includes a plurality of inputs and a plurality of outputs, a respective output of the demultiplexer being in communication with the input of a respective one of the AND gates for selectively enabling a respective one of the AND gate in response to the state of the control signals.

대표청구항 ▼

An improved data encryption system having a 64-bits second stage data encryption engine in combination with a microcontrol system, wherein said data encryption system is in electrical communication with said microcontrol system for receiving control signals from said microcontrol system and wherein

An improved data encryption system having a 64-bits second stage data encryption engine in combination with a microcontrol system, wherein said data encryption system is in electrical communication with said microcontrol system for receiving control signals from said microcontrol system and wherein the improvement comprises a first stage including: an 8-bit bus input and 64-bits output from said first stage to said second stage data encryption engine; a plurality of 8-bit registers; a plurality of AND gates having a respective input in communication with said 8-bit bus and respective output from each of said AND gate directed to a respective input of one of said 8-bit registers for selectively gating data from said 8-bit bus to respective ones of said 8-bit registers; a demultiplexer having a plurality of inputs and a plurality of outputs, a respective one of said outputs of said demultiplexer being in communication with said input of a respective one of said AND gates for selectively enabling a respective one of said AND gates in response to the state of said control signals.