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Implementation of a selected instruction set CPU in programmable hardware 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/00
  • G06F-015/177
출원번호 US-0449563 (1995-05-24)
발명자 / 주소
  • Taylor Brad (Oakland CA)
출원인 / 주소
  • Giga Operations Corporation (Berkeley CA 02)
인용정보 피인용 횟수 : 90  인용 특허 : 6

초록

A method of designing a CPU for implementation in a configurable hardware device by identifying a series of operations in a logic scheme which are suitable for implementation in the device, identifying an executable function and any needed parameters in the logic scheme, identifying the logic flow i

대표청구항

A method of designing a CPU for implementation in a configurable hardware device, said method comprising: providing a logic scheme, providing a configurable hardware device, identifying a plurality of operations in a logic scheme which are suitable for implementation in said configurable hardware de

이 특허에 인용된 특허 (6)

  1. Soderbery Robert W. (San Jose CA) Dunckel Nicholas (Los Altos CA) Kuekes Philip J. (Pebble Beach CA), Crossbar switch connected modular multiprocessor system with processor timing relationship selected and synchronized to.
  2. Blahut Donald E. (Holmdel NJ) Copp David H. (Morristown NJ) Stanzione Daniel C. (Marlboro NJ), Data processing apparatus providing autoloading of memory pointer registers.
  3. Yetter Jeffry D. (Ft. Collins CO), Functionally complete family of self-timed dynamic logic circuits.
  4. Shoji Masakazu (Warren NJ), Microprocessor architecture for improved chip testability.
  5. Vandierendonck Jerry L. (Houston TX), Multi-functional arithmetic and logical unit.
  6. Agrawal Om (San Jose CA) Shankar Kapil (San Jose CA), Programmable logic device with subroutine stack and random access memory.

이 특허를 인용한 특허 (90)

  1. Goossen Emray R. ; Shema David K. ; Lippitt Carl E., Automated validation and verification of computer software.
  2. Gonzalez, Ricardo E.; Rudell, Richard L.; Ghosh, Abhijit; Wang, Albert R., Configuring a multi-processor system.
  3. Schroeder, Charles G.; Graf, Christopher F.; Nishiguchi, Ciro T.; D'Souza, Nigel G.; Baker, Daniel J.; Magruder, Thomas D., Customizing code modules of software and programmable hardware for a test instrument.
  4. Schroeder, Charles G.; Graf, Christopher F.; Nishiguchi, Ciro T.; D'Souza, Nigel G.; Baker, Daniel J.; Magruder, Thomas D., Customizing operation of a test instrument based on information from a system under test.
  5. Andrade,Hugo A.; Odom,Brian Keith; Butler,Cary Paul; Peck,Joseph E.; Petersen,Newton G., Debugging a program intended to execute on a reconfigurable device using a test feed-through configuration.
  6. Williams,Kenneth M; Wang,Albert, Defining instruction extensions in a standard programming language.
  7. Dakhil, Dani Y., Dependency checking for reconfigurable logic.
  8. Johnson,Mark B., Digital processing device with disparate magnetoelectronic gates.
  9. Miranda,Tracy; Perry,Steven, Extended custom instructions.
  10. Johnson, Scott D., Extension adapter.
  11. Johnson,Mark B., Ferromagnetic layer compositions and structures for spin polarized memory devices, including memory devices.
  12. Kelley, John; Ho, Ying-Wai, Floating-point processor with improved intermediate result handling.
  13. Ho,Ying wai; Jiang,Xing Yu, Floating-point processor with operating mode having improved accuracy and high performance.
  14. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Generating a hardware description of a block diagram model for implementation on programmable hardware.
  15. Garvey,Joseph F.; Jeffries,Clark D., Global processor resource assignment in an assembler.
  16. Kodosky,Jeffrey L.; Andrade,Hugo; Odom,Brian K.; Butler,Cary P., Graphical program having a timing specification and method for conversion into a hardware implementation.
  17. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Graphical program with various function icons and method for conversion into hardware implementation.
  18. Dye, Robert E.; Shah, Darshan; Rogers, Steve; Richardson, Greg; Luick, Dean A., Graphical programming system with block diagram execution and distributed user interface display.
  19. Dye, Robert E.; Shah, Darshan; Rogers, Steve; Richardson, Greg; Luick, Dean A., Graphical programming system with distributed block diagram execution and front panel display.
  20. Johnson Mark B., High density and high speed magneto-electronic logic family.
  21. Johnson Mark B., High density and high speed magneto-electronic logic family.
  22. Johnson Mark B., Hybrid hall effect memory device and method of operation.
  23. Johnson, Mark B., Hybrid semiconductor-magnetic device and method of operation.
  24. Johnson, Mark B., Hybrid semiconductor?magnetic spin based memory with low transmission barrier.
  25. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Implementing a data flow block diagram having a control flow node on a programmable hardware element.
  26. Kodosky,Jeffrey L.; Andrade,Hugo; Odom,Brian K.; Butler,Cary P., Implementing a model on programmable hardware.
  27. Frank, Steven J.; Reback, Larry, Infinite memory fabric streams and APIS.
  28. Williams,Kenneth Mark; Johnson,Scott Daniel; McNamara,Bruce Saylors; Wang,Albert RenRui, Instruction set for efficient bit stream and byte stream I/O.
  29. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
  30. Gonzalez,Ricardo E.; Johnson,Scott; Taylor,Derek, Long instruction word processing with instruction extensions.
  31. Johnson,Mark B., Magnetic field sensor using spin polarized current.
  32. Johnson,Mark B., Magnetic memory device structure.
  33. Johnson,Mark B., Magnetic spin based memory with inductive write lines.
  34. Johnson,Mark B., Magnetic spin based memory with semiconductor selector.
  35. Johnson, Mark B., Magnetoelectronic device with variable magnetic write field.
  36. Johnson Mark B., Magnetoelectronic memory array.
  37. Johnson, Mark B., Magnetoelectronic memory element with inductively coupled write wires.
  38. Johnson, Mark B., Magnetoelectronic memory element with inductively coupled write wires.
  39. Johnson,Mark B., Magnetoelectronic memory element with inductively coupled write wires.
  40. Mark B. Johnson, Magnetoelectronic memory element with isolation element.
  41. Frank, Steven J.; Reback, Larry, Memory fabric operations and coherency using fault tolerant objects.
  42. Frank, Steven J.; Reback, Larry, Memory fabric software implementation.
  43. Master Paul L. ; Hatley William T. ; Scheuermann II Walter J. ; Goodman Margaret J., Method and apparatus for adaptable digital protocol processing.
  44. Jiang, XingYu; Ho, Ying-wai; Kelley, John L., Method and apparatus for predicting floating-point exceptions.
  45. Mark B. Johnson, Method of making a magnetoelectronic device.
  46. Mark B. Johnson, Method of operating a magnetoelectronic device.
  47. Johnson,Mark B., Method of operating a stacked spin based memory.
  48. Miranda, Tracy; Perry, Steven, Methods and apparatus for executing extended custom instructions.
  49. Bisinella, Richard, Microprocessor.
  50. Johnson, Mark B., Multi-bit spin memory.
  51. Kassas, Zaher; Lewis, James M., Multi-channel algorithm infrastructure for programmable hardware elements.
  52. Frank, Steven J.; Reback, Larry, Object memory interfaces across shared links.
  53. Thekkath, Radhika; Uhler, G. Michael; Ho, Ying-wai; Harrell, Chandlee B., Processor having a compare extension of an instruction set architecture.
  54. Thekkath,Radhika; Uhler,G. Michael; Ho,Ying wai; Harrell,Chandlee B., Processor having a compare extension of an instruction set architecture.
  55. Thekkath, Radhika; Uhler, G. Michael; Ho, Ying-wai; Harrell, Chandlee B., Processor having a conditional branch extension of an instruction set architecture.
  56. Thekkath, Radhika; Uhler, G. Michael; Ho, Ying-wai; Harrell, Chandlee B., Processor having an arithmetic extension of an instruction set architecture.
  57. Ho, Ying-wai; Kelley, John L.; Jiang, XingYu, Processor with improved accuracy for multiply-add operations.
  58. Ho,Ying wai; Kelley,John L.; Jiang,XingYu, Processor with improved accuracy for multiply-add operations.
  59. Arnold, Jeffrey Mark; Banta, Gareld Howard; Johnson, Scott Daniel; Wang, Albert R., Programmable logic configuration for instruction extensions.
  60. Arnold, Jeffrey Mark; Banta, Gareld Howard; Johnson, Scott Daniel; Wang, Albert R., Reconfigurable instruction set computing.
  61. Odom,Brian Keith; Peck,Joseph E.; Andrade,Hugo A.; Butler,Cary Paul; Truchard,James J.; Petersen,Newton G.; Novacek,Matthew, Reconfigurable measurement system utilizing a programmable hardware element and fixed hardware resources.
  62. Andrade,Hugo A.; Odom,Brian Keith; Ryan,Arthur, Reconfigurable test system.
  63. Ryan Arthur ; Andrade Hugo, Reconfigurable test system.
  64. Schultz, Kevin L.; Steger, Perry; Breyer, Stefanie, Smart camera with a plurality of slots for modular expansion capability through a variety of function modules connected to the smart camera.
  65. Schultz,Kevin L.; Steger,Perry; Breyer,Stefanie, Smart camera with a plurality of slots for modular expansion capability through a variety of function modules connected to the smart camera.
  66. Schultz, Kevin L.; Steger, Perry; Breyer, Stefanie, Smart camera with modular expansion capability including a function module that performs image processing.
  67. Metzgen, Paul, Software-to-hardware compiler with symbol set inference analysis.
  68. Metzgen, Paul, Software-to-hardware compiler with symbol set inference analysis.
  69. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Specifying and targeting portions of a graphical program for execution by multiple targets.
  70. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Specifying and targeting portions of a graphical program for real-time response.
  71. Kodosky,Jeffrey L.; Andrade,Hugo; Odom,Brian K.; Butler,Cary P., Specifying portions of a graphical program for respective execution by a processor and a programmable hardware element.
  72. Johnson,Mark B., Spin based device with low transmission barrier.
  73. Johnson,Mark B., Spin based electronic device.
  74. Johnson,Mark B., Spin based magnetic sensor.
  75. Johnson,Mark B., Spin based memory coupled to CMOS amplifier.
  76. Johnson,Mark B., Spin based sensor device.
  77. Johnson, Mark B., Spin memory with write pulse.
  78. Johnson, Mark B., Stacked hybrid semiconductor-magnetic spin based memory.
  79. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., System and method for configuring a device to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
  80. Chandhoke, Sundeep; Vazquez, Nicolas; Schultz, Kevin L., System and method for configuring a hardware device to execute a prototype.
  81. Peck,Joseph E.; Novacek,Matthew; Andrade,Hugo A.; Petersen,Newton G., System and method for configuring a reconfigurable system.
  82. Kodosky Jeffrey L. ; Andrade Hugo ; Odom Brian K. ; Butler Cary P., System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
  83. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian Keith; Butler, Cary Paul; Schultz, Kevin L., System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
  84. Kodosky,Jeffrey L.; Andrade,Hugo; Odom,Brian K.; Butler,Cary P., System and method for converting a graphical program including a structure node into a hardware implementation.
  85. Schultz, Kevin L.; Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian Keith; Butler, Cary Paul, System and method for deploying a graphical program on an image acquisition device.
  86. Ho, Ying-wai; Schulte, Michael J.; Kelley, John L., System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit.
  87. Gonzalez, Ricardo E.; Wang, Albert R., Systems and methods for selecting input/output configuration in an integrated circuit.
  88. Gonzalez, Ricardo E.; Wang, Albert R.; Banta, Gareld Howard, Systems and methods for software extensible multi-processing.
  89. Ilic, Kosta; Blasig, Dustyn K., Testing a graphical program intended for a programmable hardware element.
  90. Arnold,Jeffrey Mark; Banta,Gareld Howard; Johnson,Scott Daniel; Wang,Albert R., Video processing system with reconfigurable instructions.
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