Implementation of a selected instruction set CPU in programmable hardware
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/00
G06F-015/177
출원번호
US-0449563
(1995-05-24)
발명자
/ 주소
Taylor Brad (Oakland CA)
출원인 / 주소
Giga Operations Corporation (Berkeley CA 02)
인용정보
피인용 횟수 :
90인용 특허 :
6
초록▼
A method of designing a CPU for implementation in a configurable hardware device by identifying a series of operations in a logic scheme which are suitable for implementation in the device, identifying an executable function and any needed parameters in the logic scheme, identifying the logic flow i
A method of designing a CPU for implementation in a configurable hardware device by identifying a series of operations in a logic scheme which are suitable for implementation in the device, identifying an executable function and any needed parameters in the logic scheme, identifying the logic flow in the scheme, providing for at least two connected system resources to implement the logic scheme, selecting an op code, and providing a way to implement the various components needed to call and execute the function according to the logic scheme. A useful op code may invoke a system resource, implement the logic scheme, pass a parameter to the function, or invoke the function. The configurable hardware system can function as a CPU, using logic resources including a next address RAM, one or more registers, a function execution controller, and one or more busses for passing signals and data between the components and functions.
대표청구항▼
A method of designing a CPU for implementation in a configurable hardware device, said method comprising: providing a logic scheme, providing a configurable hardware device, identifying a plurality of operations in a logic scheme which are suitable for implementation in said configurable hardware de
A method of designing a CPU for implementation in a configurable hardware device, said method comprising: providing a logic scheme, providing a configurable hardware device, identifying a plurality of operations in a logic scheme which are suitable for implementation in said configurable hardware device, identifying an executable function in said logic scheme, identifying a parameter, if any, required for said executable function, identifying the logic flow in said scheme and providing for at least two connected, configurable system resources, each of selected size, to implement said logic scheme, selecting an op code of configurable, selected size to control said executable function, and providing a way to implement in configurable hardware: each of said connected, configurable system resources, a means to provide any needed parameter to said executable function, a means to pass said op code to said system resources, and a means to call said executable function, where said op code is selected from the group consisting of an op code to invoke at least one of said system resources and implement said logic scheme, an op code to pass a parameter to said executable function, and an op code to invoke said executable function.
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이 특허에 인용된 특허 (6)
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