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Interrupt for a protected mode microprocessor which facilitates transparent entry to and exit from suspend mode

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-001/32
출원번호 US-0173380 (1993-12-23)
발명자 / 주소
  • Foster Mark J. (Lincoln Township
  • Berrien County MI) Fakhruddin Saifuddin T. (St. Joseph MI) Walker James L. (Benton Harbor MI) Mendelow Matthew B. (St. Joseph MI) Sun Jiming (St. Joseph MI) Brahman
출원인 / 주소
  • Vantus Technologies, Inc. (Deerfield IL 02)
인용정보 피인용 횟수 : 29  인용 특허 : 64

초록

A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of ope

대표청구항

An apparatus, comprising: a processor having first and second operational modes, wherein in said first operational mode said processor has a predetermined set of operational capabilities and in said second operational mode said processor can perform a first subset of said operational capabilities an

이 특허에 인용된 특허 (64)

  1. Arroyo Ronald X. (Elgin TX) Day Michael N. (Austin TX) Edrington Jimmie D. (Georgetown TX) Hanna James T. (Austin TX) Hunt Gary T. (Austin TX) Pancoast Steven T. (Austin TX), Apparatus and method for suspending and resuming software applications on a computer.
  2. Hanaoka Masaaki (Suwa JPX), Apparatus for providing continuity of operation in a computer.
  3. Carter Robert R. (Cypress TX) Garner Paul M. (The Woodlands TX) Cepulis Darren J. (Houston TX) Boone Carrie (Houston TX), Apparatus for reducing computer system power consumption.
  4. Canova ; Jr. Francis J. (Boynton Beach FL) Katz Neil A. (Parkland FL) Pollitt Richard F. (Jensen Beach FL) Suarez Leopoldo L. (Boca Raton FL) Astarabadi Shaun (Irvine CA) Frank C. William (Irvine CA), Battery operated computer power management system.
  5. Pusic Vladi (San Jose CA) George Benjamin T. (Sunnyvale CA) Smith Monte E. (St. Paul MN) Johnson Craig B. (Shoreview MN), Cache/disk file status indicator with data protection feature.
  6. Tamaki Kazuyoshi (Nagoya JPX), Circuit arrangement for preventing a microcomputer from malfunctioning.
  7. Lies Kenneth A. (Lubbock TX), Clocked logic low power standby mode.
  8. Rose Frederick A. (Rte. 3 ; Box 529 Fort Atkinson WI 53538) DeWitt Christopher P. (Rte. 3 ; Koshkonong Lake Rd. Fort Atkinson WI 53538), Communications management system having multiple power control modes.
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  10. Marrington S. Paul (P.O. Box 34 Fyshwick CA AUX 2609) Kiankhooy-Fard Paul (1165 Archer St. San Diego CA 92109) Zecos Paul (13367 Caminito Mar Villa Del Mar CA) Rudaw Geoffrey (43 Argow Pl. Nanuet NY , Computer power system.
  11. Kaneda Saburo (Yokohama JPX) Murakami Kazuaki (Kawasaki JPX), Computer system for controlling virtual machines.
  12. Nagasawa Kunihiko (Tokyo JPX), Computer system with a back-up power supply.
  13. Kardach James (San Jose CA) Mathews Gregory (Cupertino CA) Nguyen Cau (Milpitas CA) Cho Sung S. (Sunnyvale CA) Sivamani Kameswaran (Sunnyvale CA) Vannier David (Cupertino CA) Wong Shing (Cupertino CA, Computer system with interrupts transparent to its operating system and application programs.
  14. Satoh Masaharu (Nara JPX) Hashimoto Sadakatsu (Nara JPX), Control system for multi-processor.
  15. Hillion Herv (Eindhoven NLX), Data processing apparatus with energy saving clocking device.
  16. McAnlis James C. (Bangor GB5) Kumar Kuldip (Gateshead PA GB2) Gould Robert T. M. (Downington PA), Data processor system including data-save controller for protection against loss of volatile memory information during p.
  17. Bush Kenneth L. (Cypress TX) Perry Ralph S. (Houston TX), Disk drive activity indicator.
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  19. Saitou Yosio (Oome JPX), Display panel open/closed detection mechanism, and portable electronic apparatus using the same.
  20. Swartz Jack S. (San Jose CA), Dual mode actuator for disk drive useful with a portable computer.
  21. Garner Paul M. (The Woodlands TX) Boone Carrie (Houston TX) Cepulis Darren J. (Houston TX), Dynamically configurable portable computer system.
  22. Kimura Toshiyuki (Kawagoe JPX) Yamazaki Youichi (Kawagoe JPX) Nonaka Yoshiya (Kawagoe JPX) Go Yasunao (Kawagoe JPX) Endo Fumio (Kawagoe JPX) Komata Hiroyuki (Kawagoe JPX) Syoji Mitsuo (Kawagoe JPX), Electronic unit operable in conjunction with body unit.
  23. Poret Mark (Mesa AZ) McKinley Jeanne (Chandler AZ), In-circuit emulator.
  24. Suzuki Naoshi (Kanagawa JPX) Uno Shunya (Machida JPX), Information processing system having power saving control of the processor clock.
  25. Little Wendell L. (Carrollton TX), Integrated circuit with watchdog timer and sleep control logic which places IC and watchdog timer into sleep mode.
  26. Yorimoto Yoshikazu (Tokyo JPX) Takahashi Masashi (Tokyo JPX) Hirano Seiji (Tokyo JPX), Integrated-circuit card with active mode and low power mode.
  27. Adams Matthew K. (Dallas TX) Little Wendell L. (Denton TX) Grider Stephen N. (Farmers Branch TX), Interface: interrupt masking with logical sum and product options.
  28. Raasch Charles F. (El Toro CA) Kim Jason S. M. (Los Angeles CA), Internal interrupt controller for a peripheral controller.
  29. James David V. (Palo Alto CA), Interrupt system using masking register in processor for selectively establishing device eligibility to interrupt a part.
  30. Takayama Shigeru (Tokyo JPX), Interruption control circuit.
  31. Bartling James E. (Dallas TX) Little Wendell L. (Denton TX) Deierling Kevin E. (Dallas TX), Isolation gates to permit selective power-downs within a closely-coupled multi-chip system.
  32. Jones Steven W. (Wood Dale IL) Alifen Chandra (Hoffman Estates IL), Line power failure scheme for a gaming device.
  33. Cole James F. (Palo Alto CA) McNamara James H. (Santa Cruz CA), Low-power, standby mode computer.
  34. Cole James F. (Palo Alto CA) McNamara James H. (Santa Cruz CA), Low-power, standby mode computer.
  35. Nishimura Kosuke (Yamatokoriyama JPX), Memory contents confirmation.
  36. Belt Steven L. (Stevensville MI) Ruthenbeck Mark A. (Lincoln Township ; Berrien County MI) Foster Mark J. (Lincoln Township ; Berrien County MI) Barnes Brian C. (Benton Township ; Berrien County MI) , Method and apparatus facilitating communication between two keyboards and a single processor.
  37. Fakhruddin Saifuddin T. (St. Joseph MI) Foster Mark J. (Lincoln Township ; Berrien County MI) Hovey Scott A. (St. Joseph MI) Walker James L. (Benton Harbor MI) Vanderheyden Randy J. (St. Joseph Towns, Method and apparatus facilitating use of a hard disk drive in a computer system having suspend/resume capability.
  38. Fakruddin Saifee (St. Joseph MI) Foster Mark J. (Stevensville MI), Method and apparatus for battery-power management using load-compensation monitoring of battery discharge.
  39. Letwin James (Kirkland WA), Method and operating system for executing programs in a multi-mode microprocessor.
  40. Watanabe Minoru (Tokyo JPX), Microcomputer which enters sleep mode for a predetermined period of time on response to an activity of an input/output d.
  41. Arroyo Ronald X. (Elgin TX) Hanna James T. (Austin TX), Multi-frequency clock generation with low state coincidence upon latching.
  42. Yurchenco James R. (Palo Alto CA), Multiple independent input peripherals.
  43. Hirano Takaaki (Nara JPX) Kamuro Setsufumi (Yamatokoriyama JPX) Yamaguchi Akira (Nara JPX) Tanimoto Junichi (Tenri JPX) Okada Mikiro (Nara JPX), Peripheral unit for a microprocessor system.
  44. Kobayashi Takaichi (Itsukaichi JPX), Personal computer having condition indicator.
  45. Murez James D. (Santa Monica CA), Portable computer enclosure.
  46. Fung Henry T. S. (San Jose CA), Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system.
  47. Perry Richard A. (Charlotte NC) Stant Vernon L. (Richmond VA), Power conservation in microprocessor controlled devices.
  48. Zato Thomas J. (Palatine IL), Power loss compensation for programmable memory control system.
  49. Smith R. Steven (Saratoga CA) Hanlon Mike S. (San Jose CA) Bailey Robert L. (San Jose CA), Power management for a laptop computer with slow and sleep modes.
  50. Juzswik David L. (Dearborn Heights MI) Webb Nathaniel (Detroit MI) Floyd William M. (Livonia MI), Power-conserving control system for turning-off the power and the clocking for data transactions upon certain system ina.
  51. Culley Paul R. (Houston TX), Priority arbitration circuit for processor access.
  52. Mori Shosuke (Tokyo JPX), Processor having plural initial loading programs for loading different operating systems.
  53. Watts ; Jr. LaVaughn F. (Temple TX) Wallace Steven J. (Temple TX), Real-time power conservation for portable computers.
  54. Arai Makoto (Tokyo JPX), Resume control system and method for executing resume processing while checking operation mode of CPU.
  55. Niijima Shinji (Tokyo JPX), Single-chip mircocomputer with clock-signal switching function which can disable a high-speed oscillator to reduce power.
  56. Reddy Chandrashekar M. (Santa Clara CA) Hirose Scott D. (San Jose CA) Cho Sung-Soo (Sunnyvale CA) Kardach James P. (San Jose CA) Farrer Steven M. (Santa Clara CA) Roberts Meeling (Fremont CA), Slow memory refresh in a computer with a limited supply of power.
  57. Nocilini, John D.; Sharp, Ronald E.; Cuadra, Emilio J., Stanby mode controller utilizing microprocessor.
  58. Nguyen Au H. (Santa Clara CA) Gollabinnie Aurav R. (San Jose CA), Suspend/resume apparatus and method for reducing power consumption in battery powered computers.
  59. Lee Robert H. J. (Palo Alto CA) Kenny John D. (Sunnyvale CA), Switchable clock circuit for microprocessors to thereby save power.
  60. Chang Bo E. (22 Yearling Ct. Rockville MD 20850), Three layered laptop computer.
  61. Kardach James (San Jose CA) Mathews Gregory (Cupertino CA) Nguyen Cau (Milpitas CA) Cho Sung S. (Sunnyvale CA) Sivamani Kameswaran (Sunnyvale CA) Vannier David (Cupertino CA) Wong Shing (Cupertino CA, Transparent system interrupt.
  62. Byrd Kerry (Falls Church VA), Work-saving system for preventing loss in a computer due to power interruption.
  63. Alley Lynn D. (Riverton UT) Alley Stephen W. (Bountiful UT) Sadlier William K. (Salt Lake City UT) Burton Richard A. (Salt Lake City UT), Wrap-around auxiliary keyboard.
  64. Director Dennis (3116 Central St. Evanston IL 60201), Write protect control circuit for computer hard disc systems.

이 특허를 인용한 특허 (29)

  1. Chidester Philip Dale, Computer system having a controller which emulates a peripheral device during initialization.
  2. Ninomiya Ryoji,JPX ; Nakamura Koji,JPX, Computer system in which a high-order application program recognizes a power-on factor or a state of an expansion unit.
  3. Onishi Satoshi,JPX ; Kubo Yukihiro,JPX ; Kimura Kozue,JPX ; Nishida Osamu,JPX, Conversational sentence translation apparatus allowing the user to freely input a sentence to be translated.
  4. Galbi,Duane E.; Loboprabhu,Ranjit; Niell,Jose, ECC coding for high speed implementation.
  5. Muir, Robert Lindley; Boesen, John; Jones, Mike, Gaming machine power fail enhancement.
  6. Muir, Robert Lindley; Boesen, John; Jones, Mike, Gaming machine power fail enhancement.
  7. Muir, Robert Lindley; Boesen, John; Jones, Mike, Gaming machine power fail enhancement.
  8. Baweja Gunjeet, Maintaining a memory while in a power management mode.
  9. Purang, Khemdut; Plutowski, Mark Earl, Method and apparatus for an itinerary planner.
  10. Purang, Khemdut; Plutowski, Mark Earl, Method and apparatus for an itinerary planner.
  11. Baweja Gunjeet, Method and apparatus for logic and power isolation during power management.
  12. Christensen Alan ; Kocher Fritz, Method and apparatus for preventing inadvertent power management time-outs.
  13. Vu, Son Trung; Phan, Quang, Method and apparatus for secure processing of cryptographic keys.
  14. Blank Felix,DEX ; Schicklinski Peter,DEX ; Sterr Bettina,DEX ; Wiesinger Ursula,DEX, Method for managing interrupt signals in a real-time computer system.
  15. Brett Louis Lindsley, Method, device and article of manufacture for efficient task scheduling in a multi-tasking preemptive priority-based real-time operating system.
  16. Takahashi, Masafumi, Microprocessor including memory for storing set value used to select and executive instruction after completing exception handling caused by exception request.
  17. White Dave ; Lee Yen Wei ; Ang Rod ; Barbieri Ray ; Chen James,TWX ; Lee Suh Chiueh, Power management system for a computer.
  18. White Dave ; Lee Yen Wei ; Ang Rod ; Barbieri Ray ; Chen James,TWX ; Lee Suh Chiueh, Power mangement system for a computer.
  19. Totsuka, Yonetaro; Ishibashi, Koichiro; Mizuno, Hiroyuki; Nishii, Osamu; Uchiyama, Kunio; Shimura, Takanori; Sekine, Asako; Katsuki, Yoichi; Narita, Susumu, Processor for controlling substrate biases in accordance to the operation modes of the processor.
  20. Fleischmann, Marc; Anvin, H. Peter, Restoring processor context in response to processor power-up.
  21. Cox, Alan, Rights management system.
  22. Sonobe Masayuki,JPX, Secret information protection system.
  23. Totsuka, Yonetaro; Ishibashi, Koichiro; Mizuno, Hiroyuki; Nishii, Osamu; Uchiyama, Kunio; Shimura, Takanori; Sekine, Asako; Katsuki, Yoichi; Narita, Susumu, Substrate bias switching unit for a low power processor.
  24. Totsuka,Yonetaro; Ishibashi,Koichiro; Mizuno,Hiroyuki; Nishii,Osamu; Uchiyama,Kunio; Shimura,Takanori; Sekine,Asako; Katsuki,Yoichi; Narita,Susumu, Substrate bias switching unit for a low power processor.
  25. Khouli Sami ; Mughir Taha ; Nelson Albert Rudy, Supplying standby voltage to memory and wakeup circuitry to wake a computer from a low power mode.
  26. George Chrysanthakopoulos, System and method for handling power state change requests initiated by peripheral devices.
  27. Fleischmann, Marc; Anvin, H. Peter, System and method for saving and restoring a processor state without executing any instructions from a first instruction set.
  28. Truong Cuong Cam, System for powering down a portable computer in a docking station.
  29. Ervin,Joseph James, Systems and methods for addressing memory.
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