초록 ▼

A DSP co-processor (72) that is used on an integrated circuit (24) that provides multiple communication functions is accomplished by providing a data bus interface (320), a sequencer (328), internal memory (33), and a data core (322). The sequencer (328) stores in a hardware format a signal processi

A DSP co-processor (72) that is used on an integrated circuit (24) that provides multiple communication functions is accomplished by providing a data bus interface (320), a sequencer (328), internal memory (33), and a data core (322). The sequencer (328) stores in a hardware format a signal processing algorithm (332) and, upon receipt of an operational command, provides address control signals (334) and operation control signals (336) to the data core (322). The data core (322), which includes an address generation unit (340) and an arithmetic unit (344), executes, via the arithmetic unit, operational instructions of the signal processing algorithm to produce resultant signals from the input samples, the intermediate resultants, and the algorithm co-efficients.

대표청구항 ▼

A co-processor for use with a digital signal processor, the co-processor comprising: first data bus interface that transports first data to and from an external memory source via a dedicate data bus; second data bus interface that transports, via a general purpose data bus, an operational command fr

A co-processor for use with a digital signal processor, the co-processor comprising: first data bus interface that transports first data to and from an external memory source via a dedicate data bus; second data bus interface that transports, via a general purpose data bus, an operational command from an external source and second data to and from at least the external memory or the external source; a plurality of registers, wherein each of the plurality of registers is operably coupled to the first data bus interface and the second data bus interface, and wherein at least one of the plurality of registers temporarily stores at least a portion of the first data; sequencer that is operably coupled to the second data bus interface, wherein the sequencer stores, in a hardware format, a signal processing algorithm, wherein the sequencer, upon receipt of the operational command, at recurring instruction intervals, at least an address control signal and an operation control signal, wherein the address control signal and the operation control signal govern execution of the signal processing algorithm; address generation unit that is operably coupled to the first data bus interface and the sequencer, wherein the address generation unit provides an address to the external memory based on the address control signal, such that the first data is retrieved from the external memory; and arithmetic logic unit that is operably coupled to the sequencer and the plurality of registers, wherein the arithmetic logic unit accumulatively executes, based on the operation control signal, operational instructions of the signal processing algorithm to produce a resultant signal from the first data.