초록 ▼

A method for fabricating a self-aligned thin-film transistor, in accordance with the present invention, first involves forming a gate electrode on an insulating layer. Next, a gate dielectric layer is formed to enclose the gate electrode. Subsequently, a semiconductor layer, a conducting layer, and

A method for fabricating a self-aligned thin-film transistor, in accordance with the present invention, first involves forming a gate electrode on an insulating layer. Next, a gate dielectric layer is formed to enclose the gate electrode. Subsequently, a semiconductor layer, a conducting layer, and a first dielectric layer are formed to cover the substrate and the gate dielectric layer. Afterwards, a chemical mechanical polishing process is applied to subsequently polish the first dielectric layer and the conducting layer to expose the semiconductor layer above the gate electrode. Therefore, the conducting layer disposed at opposite sides of the gate electrode is self-aligned to act as the source/drain regions of the fabricated TFT device.

대표청구항 ▼

A method for fabricating a thin-film transistor, comprising: providing an insulating substrate; forming a gate electrode on said substrate; forming a gate dielectric layer covering said gate electrode; subsequently forming a semiconductor layer and a conducting layer overlying said substrate as well

A method for fabricating a thin-film transistor, comprising: providing an insulating substrate; forming a gate electrode on said substrate; forming a gate dielectric layer covering said gate electrode; subsequently forming a semiconductor layer and a conducting layer overlying said substrate as well as said gate dielectric layer; forming a first dielectric layer on said conducting layer; subsequently polishing said first dielectric layer and conducting layer to expose said semiconductor layer above said gate electrode; forming a second dielectric layer on said first dielectric layer and said exposed semiconductor layer; forming a pair of contact windows through said second and first dielectric layers to expose said conducting layer disposed at opposite sides of said gate electrode; and forming a pair of source/drain electrodes to connect said exposed conducting layer via said contact windows, respectively.