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Method for forming an aluminum contact through an insulating layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/441
출원번호 US-0159448 (1993-11-30)
발명자 / 주소
  • Lin Yih-Shung (Plano TX) Liou Fu-Tai (Carrollton TX)
출원인 / 주소
  • SGS-Thomson Microelectronics, Inc. (Carrollton TX 02)
인용정보 피인용 횟수 : 29  인용 특허 : 21

초록

A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refra

대표청구항

A method for forming an interlevel aluminum contact for an integrated circuit device, comprising the steps of: forming an opening through an insulating layer to expose a conducting structure; forming a barrier layer over the insulating layer and extending into the opening to cover the conducting str

이 특허에 인용된 특허 (21)

  1. Ryan Vivian W. (Nutley NJ) Schutz Ronald J. (Warren NJ), Aluminum metallization for semiconductor devices.
  2. Mintz Donald M. (Sunnyvale CA), Apparatus and method for manufacturing planarized aluminum films.
  3. Lamont ; Jr. Lawrence T. (San Jose CA) Mosely Roderick C. (Mountain View CA) McEntee Timothy M. (Milpitas CA), Deposition and planarizing methods and apparatus.
  4. Lu Toh-Ming (Latham NY) Mei Shao-Ning (Wappingers Falls NY), Deposition of metals on stepped surfaces.
  5. van de Ven Everhardus P. G. T. (Muko CA JPX) Towner Janet M. (Palo Alto CA), Formation of electromigration resistant aluminum alloy conductors.
  6. Eizenberg Moshe (Kiryat-Ata NJ ILX) Murarka Shyam P. (New Providence NJ), Forming low-resistance contact to silicon.
  7. Magee Thomas J. (Belmont CA) Osborne John F. (Sunnyvale CA) Gildea Peter (Sunnyvale CA) Leung Charles H. (San Jose CA), Laser planarization of nonrefractory metal during integrated circuit fabrication.
  8. Cheung Robin W. (Cupertino CA) Ho Bernard W. K. (Fremont CA) Chen Hsiang-Wen (Cupertino CA) Chan Hugo W. K. (Fremont CA), Making a low resistance three layered contact for silicon devices.
  9. Yamamoto Hiroshi (Neyagawa JPX) Fujita Tsutomu (Hirakata JPX) Kakiuchi Takao (Takarazuka JPX) Yano Kousaku (Osaka JPX) Tanimura Shuichi (Hirakata JPX) Fujii Shinji (Hirakata JPX), Method for fabricating interconnection structure.
  10. Chen Fusen E. (Dallas TX) Liou Fu-Tai (Carrollton TX) Lin Yih-Shung (Carrollton TX) Dixit Girish A. (Dallas TX) Wei Che-Chia (Plano TX), Method for forming a metal contact.
  11. Penning De Vries RenG. M. (Eindhoven NLX), Method of establishing an interconnection level on a semiconductor device having a high integration density.
  12. Deleonibus Simon (Grenoble FRX) Dubois Guy (St. Etienne de Crossey FRX), Method of fabrication of aluminum contacts through a thick insulating layer in an integrated circuit.
  13. Inoue Minoru (Kawasaki JPX), Method of forming a barrier layer between a silicon substrate and an aluminum electrode of a semiconductor device.
  14. Maydan Dan (Los Altos Hills CA) Somekh Sasson (Redwood City CA) Wang David N. (Cupertino CA) Cheng David (San Jose CA) Toshima Masato (San Jose CA) Harari Isaac (Mountain View CA) Hoppe Peter D. (Sun, Multi-chamber integrated process system.
  15. Schilling ; Hartmut, Multilayer interconnected structure for semiconductor integrated circuit.
  16. Saxena Arjun N. (4217 Pomona Ave. Palo Alto CA 94306), Multilevel metallization process for integrated circuits.
  17. Tracy Clarence J. (Tempe AZ) Freeman ; Jr. John L. (Mesa AZ) Duffin Robert L. (Mesa AZ) Polito Anthony (Mesa AZ), Multiple step metallization process.
  18. Wang Chien-Rhone (Milpitas CA), Multistep sputtering process for forming aluminum layer over stepped semiconductor wafer.
  19. Armstrong Karl J. (Congers NY) Aronson Arnold J. (Pomona NY) Roberts Jon A. (Suffern NY), Planarization method.
  20. Scovell Peter D. (Chelmsford GB2) Rosser Paul J. (Harlow GB2) Tomkins Gary J. (Braintree GB2), Process of self aligned nitridation of TiSi2 to form TiN/TiSi2 contact.
  21. Polito Anthony (Mesa AZ) Pages Irenee M. (Chandler AZ), Semiconductor device metallization process.

이 특허를 인용한 특허 (29)

  1. Lin Hsiang-Lin,TWX ; Chen Han-Chung,TWX, Add one process step to control the SI distribution of Alsicu to improved metal residue process window.
  2. Satitpunwaycha Peter ; Yao Gongda ; Ngan Kenny King-Tai ; Xu Zheng, Aluminum hole filling method using ionized metal adhesion layer.
  3. Lee,Wei Ti; Guo,Ted; Yu,Sang Ho, Aluminum sputtering while biasing wafer.
  4. Xu Zheng ; Forster John ; Yao Tse-Yong, Apparatus for filling apertures in a film layer on a semiconductor substrate.
  5. Xu Zheng ; Forster John ; Yao Tse-Yong ; Nulman Jaim ; Chen Fusen, Filling narrow apertures and forming interconnects with a metal utilizing a crystallographically oriented liner layer.
  6. Restaino Darryl ; Yang Chi-Hua ; Poetzlberger Hans W.,DEX ; Katata Tomio,JPX ; Aochi Hideaki, High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring.
  7. Satitpunwaycha Peter ; Yao Gongda ; Ngan Kenny King-Tai ; Xu Zheng, Integrated PVD system for aluminum hole filling using ionized metal adhesion layer.
  8. Ding, Peijun; Xu, Zheng; Zhang, Hong; Tang, Xianmin; Gopalraja, Praburam; Rengarajan, Suraj; Forster, John C.; Fu, Jianming; Chiang, Tony; Yao, Gongda; Chen, Fusen E.; Chin, Barry L.; Kohara, Gene Y., Metal / metal nitride barrier layer for semiconductor device applications.
  9. Naik Mehul B. ; Guo Ted ; Chen Liang-Yuh ; Mosely Roderick Craig ; Beinglass Israel, Metallization process and method.
  10. Sidhwa, Ardeshir J., Method and structure of a thick metal layer using multiple deposition chambers.
  11. Lau, Gorley L., Method for forming a metallization structure in an integrated circuit.
  12. Gorley L. Lau, Method for forming void-free metallization in an integrated circuit.
  13. Xu Zheng ; Forster John ; Yao Tse-Yong, Method for low thermal budget metal filling and planarization of contacts vias and trenches.
  14. Chiang,Tony; Yao,Gongda; Ding,Peijun; Chen,Fusen E.; Chin,Barry L.; Kohara,Gene Y.; Xu,Zheng; Zhang,Hong, Method of depositing a metal seed layer on semiconductor substrates.
  15. Chiang,Tony; Yao,Gongda; Ding,Peijun; Chen,Fusen E.; Chin,Barry L.; Kohara,Gene Y.; Xu,Zheng; Zhang,Hong, Method of depositing a metal seed layer on semiconductor substrates.
  16. Ding,Peijun; Xu,Zheng; Zhang,Hong; Tang,Xianmin; Gopalraja,Praburam; Rengarajan,Suraj; Forster,John C.; Fu,Jianming; Chiang,Tony; Yao,Gongda; Chen,Fusen E.; Chin,Barry L.; Kohara,Gene Y., Method of depositing a tantalum nitride/tantalum diffusion barrier layer system.
  17. Park Sang-Hoon,KRX, Method of forming a metal interconnection line for semiconductor device.
  18. Sandhu Gurtej S. ; Iyer Ravi, Method of forming aluminum film.
  19. Lee, Ming-Han; Kuo, Tz-Jun; Ho, Chien-Hsin; Lee, Hsiang-Huan, Method of forming an interconnection.
  20. Sandhu Gurtej S. ; Iyer Ravi, Method of making a void-free aluminum film.
  21. Sandhu, Gurtej S.; Iyer, Ravi, Method of making a void-free aluminum film.
  22. Sandhu, Gurtej S.; Iyer, Ravi, Method of making a void-free aluminum film.
  23. Kuno Toyohiko,JPX ; Kitamura Kenichi,JPX ; Tanaka Ken,JPX, Method of manufacturing multiple aluminum layer in a semiconductor device.
  24. Konecni Anthony J. ; Russell Noel, PVD deposition process for CVD aluminum liner processing.
  25. Hatano, Masaaki; Usui, Takamasa, Semiconductor device.
  26. Xu Zheng ; Forster John ; Yao Tse-Yong, Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches.
  27. Laptev, Pavel N.; Felmetsger, Valery, Stress adjustment in reactive sputtering.
  28. Laptev, Pavel N; Felmetsger, Valery, Stress adjustment in reactive sputtering.
  29. Jick Yu ; Ruth Brain, Two chamber metal reflow process.

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