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A method for forming a Damascene structured multi-layered metal wiring for a semiconductor element, which includes the steps for forming a first insulating layer on the surface of a semiconductor substrate, forming a lower metal wiring pattern on the first insulating layer, forming a second insulati

A method for forming a Damascene structured multi-layered metal wiring for a semiconductor element, which includes the steps for forming a first insulating layer on the surface of a semiconductor substrate, forming a lower metal wiring pattern on the first insulating layer, forming a second insulating layer on the first insulating layer and the lower metal wiring pattern, forming contacts by subjecting the second insulating layer to etching, successively depositing first and second upper metals over the second insulating layer and the contact, subjecting the second upper metal to etching until the first upper metal is exposed, and forming an upper metal wiring pattern having a double metal structure by subjecting the first upper metal to etching until the second insulating layer is exposed. The upper wiring layer is preferably formed of aluminum deposited by a sputtering method and tungsten deposited by a chemical vapor deposition method.

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A method for forming a multi-layered metal wiring for a semiconductor element, the method comprising the steps of: forming a first insulating layer on a surface of a semiconductor substrate; forming a lower metal wiring pattern on the first insulating layer; forming a second insulating layer on the

A method for forming a multi-layered metal wiring for a semiconductor element, the method comprising the steps of: forming a first insulating layer on a surface of a semiconductor substrate; forming a lower metal wiring pattern on the first insulating layer; forming a second insulating layer on the first insulating layer and the lower metal wiring pattern; forming contact portions in the second insulating layer; successively depositing first and second upper metals over the contact portions and the second insulating layer; removing portions of the second upper metal by subjecting said second upper metal to an etch back process until the first upper metal is exposed; and removing portions of the first upper metal by subjecting said first upper metal to a chemical mechanical polishing process until the second insulating layer is exposed, thereby to form an upper metal wiring pattern comprised of the first and second upper metals.