이 특허를 인용한 특허 (74)

1. Shekhar Pramanick ; John A. Iacoponi, Alloy barrier layers for semiconductors.

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2. Moffat, William A.; McCoy, Craig Walter, Apparatus for the efficient coating of substrates.

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3. Huang, Cheng-Tang, Bump structure having a reinforcement member.

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4. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.

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5. Lin,Mou Shiung, Chip structure with redistribution traces.

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6. Akram, Salman, Copper interconnect.

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7. Akram,Salman, Copper interconnect.

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8. Akram,Salman, Copper interconnect.

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9. Akram,Salman, Copper interconnect for semiconductor device.

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10. Chen, Yen-Ming; Chu, Cheng-Yu; Lin, Kuo-Wei; Peng, Chiou-Shian; Fan, Yang-Tung; Fan, Fu-Jier; Lin, Shih-Jane, Dual layer photoresist method for fabricating a mushroom bumping plating structure.

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11. Maeda, Yukihiro; Ootani, Yuji; Nakano, Tetsuo; Nagasaka, Takashi, Electronic part mounting method.

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12. Sutardja,Sehat; Wu,Albert; Lee,Jin Yuan; Lin,Mou Shiung, Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits.

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13. Virkar, Ajay; Yang, Xiqiang; Li, Ying-Syi; McKean, Dennis; LeMieux, Melburne C., Fused metal nanostructured networks, fusing solutions with reducing agents and methods for forming metal networks.

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14. Johnson,Klein L., Hermetic chip-scale package for photonic devices.

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15. Babcock,Jeff; Darmawan,Johan Agus; Mason,John; Diep,Ly, LDMOS transistor with improved gate shield.

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16. Ignaut, Sharon L., Light barrier for light sensitive semiconductor devices.

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17. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.

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18. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.

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19. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.

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20. Akram, Salman, Method and semiconductor device having copper interconnect for bonding.

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21. Shih, Cheng-Hung; Hsieh, Yung-Wei; Lin, Shu-Chen; Lin, Cheng-Fan; Dai, Hua-An, Method for manufacturing fine-pitch bumps and structure thereof.

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22. Gutt, Thomas; Sgouridis, Sokratis, Method for producing and cleaning surface-mountable bases with external contacts.

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23. Imanishi,Makoto; Narita,Shoriki; Ikeya,Masahiko; Kanayama,Shinji; Mae,Takaharu, Method of forming bumps on a wafer utilizing a post-heating operation, and an apparatus therefore.

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24. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.

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25. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.

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26. Akram,Salman, Method of improving copper interconnects of semiconductor devices for bonding.

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27. Gottfried, Mark, Method of making an aligned electrode on a semiconductor structure.

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28. Liu Hermen,TWX ; Huang Yimin,TWX, Method of testing and packaging a semiconductor chip.

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29. Lee, Jin Yuan; Chen, Ying Chih; Lin, Mou Shiung, Method of wire bonding over active area of a semiconductor circuit.

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30. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.

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31. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.

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32. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.

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33. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.

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34. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.

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35. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.

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36. Yang-Tung Fan TW; Hsiu-Mei Yu TW; Li-Hsin Tseng TW; Kuang-Peng Lin TW; Ta-Yang Lin TW, Method to achieve robust solder bump height.

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37. Wang, Tsing-Chow, Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties.

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38. Tsing-Chow Wang ; Te-Sung Wu, Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability.

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39. Yamamoto Motohiko,JPX ; Kubo Masaru,JPX, Photodetector element containing circuit element and manufacturing method thereof.

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40. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.

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41. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.

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42. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.

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43. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.

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44. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.

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45. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.

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46. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.

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47. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.

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48. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.

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49. Kim Seong Jin,KRX, Semiconductor device having a bump structure and test electrode.

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50. Akram, Salman, Semiconductor device having copper interconnect for bonding.

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51. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.

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52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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57. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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58. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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59. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.

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60. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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61. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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62. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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63. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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64. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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65. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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66. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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67. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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68. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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69. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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70. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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71. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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72. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.

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73. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.

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74. Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Li-Ren; Lin, Chu-Fu, Wafer level processing method and structure to manufacture two kinds of interconnects, gold and solder, on one wafer.

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