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Programmable microsystems in silicon 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/06
  • H01L-021/70
출원번호 US-0367556 (1995-01-03)
발명자 / 주소
  • Dangelo Carlos (Los Gatos CA)
출원인 / 주소
  • LSI Logic (Milpitas CA 02)
인용정보 피인용 횟수 : 61  인용 특허 : 0

초록 ▼

An integrated circuit fabrication method and apparatus to improve the design cycle time for implementing an electrical system in silicon. The invention uses predefined core, or cell, patterns to provide some of the functionality for a system design. The cores are interconnected using thick wire cond

대표청구항 ▼

An integrated circuit formed on a silicon substrate, wherein the silicon substrate has a planar surface, the integrated circuit comprising: a first core formed on the planar surface of the silicon substrate, wherein the first core includes a first microcircuit with a first conductor contact; a secon

이 특허를 인용한 특허 (61)

  1. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
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  2. Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Li-Ren; Lo, Hsin-Jung, Chip package and method for fabricating the same.
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  3. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
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  4. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
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  5. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
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  6. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
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  7. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
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  8. Siniaguine, Oleg, Clock distribution networks and conductive lines in semiconductor integrated circuits.
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  9. Siniaguine,Oleg, Clock distribution networks and conductive lines in semiconductor integrated circuits.
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  10. Benjamin N. Eldridge ; Igor Y. Khandros ; David V. Pedersen ; Ralph G. Whitten, Concurrent design and subsequent partitioning of product and test die.
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  11. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
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  12. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
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  13. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
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  14. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
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  15. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
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  16. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  17. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  18. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  19. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  20. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  21. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
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  22. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
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  23. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  24. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  25. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  26. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  27. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
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  28. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
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  29. Lee Jeong-Soo,KRX, Multi-layer interconnection layout between a chip core and peripheral devices.
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  30. Harry N. Gardner ; Debra S. Harris ; Michael D. Lahey ; Stacia L. Patton ; Peter M. Pohlenz, Parameter adjustment in a MOS integrated circuit.
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  31. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  32. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  33. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  34. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  35. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  36. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
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  37. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
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  38. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
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  39. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
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  40. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
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  41. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
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  42. Ellison John J. ; Clocher Dennis Felix ; Lisowski Joseph John ; Temple Joseph L. ; Nealon Michael G., Prototyping multichip module.
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  43. Shoji, Kimikatsu; Tadokoro, Hirofumi; Yanaga, Osamu, Semiconductor integrated circuit and method of manufacturing the same.
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  44. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
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  45. Stanvick,Mark, Single layer configurable logic.
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  46. Chou, Chiu-Ming; Lin, Mou-Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
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  47. Eldridge, Benjamin N.; Khandros, Igor Y.; Pedersen, David V.; Whitten, Ralph G., Test assembly including a test die for testing a semiconductor product die.
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  48. Eldridge, Benjamin N.; Khandros, Igor Y.; Pedersen, David V.; Whitten, Ralph G., Test assembly including a test die for testing a semiconductor product die.
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  49. Eldridge, Benjamin N.; Khandros, Igor Y.; Pedersen, David V.; Whitten, Ralph G., Test assembly including a test die for testing a semiconductor product die.
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  50. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  51. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  57. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  58. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  59. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  60. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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  61. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
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