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Interconnect structures for integrated circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/52
  • H01L-023/535
출원번호 US-0487787 (1995-06-07)
발명자 / 주소
  • Chung Henry Wei-Ming (Cupertino CA)
출원인 / 주소
  • National Semiconductor Corporation (Santa Clara CA 02)
인용정보 피인용 횟수 : 41  인용 특허 : 0

초록 ▼

A multilevel interconnect structure which has a first horizontal metallic conductor disposed on the top of a previously formed first contact/via dielectric where the contact/via dielectric contains a contact/via hole. A horizontal, interconnect is deposited over the first contact/via dielectric and

대표청구항 ▼

An interconnect structure comprising: a generally horizontal interconnect, of thickness t and linewidth w, having a first portion; and a generally vertical interconnect terminating the first conductive layer and in contact with the first conductive layer first portion at an approximately vertical in

이 특허를 인용한 특허 (41)

  1. Park, Byeongju; Iyer, Subramanian S.; Kothandaraman, Chandrasekharan, Antifuse structure having an integrated heating element.
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  2. Albert Bergemont ; Alexander Kalnitsky, Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture.
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  3. Bergemont Albert ; Kalnitsky Alexander, Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture.
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  4. Ikemasu, Shinichiroh; Okawa, Narumi, Highly integrated and reliable DRAM and its manufacture.
    상세보기
  5. Ikemasu, Shinichiroh; Okawa, Narumi, Highly integrated and reliable DRAM and its manufacture.
    상세보기
  6. Harvey Ian, Integrated circuit device interconnection techniques.
    상세보기
  7. Roberts,Martin C.; Tang,Sanh D., Integrated circuit interconnect.
    상세보기
  8. Roberts,Martin C.; Tang,Sanh D., Integrated circuit using a dual poly process.
    상세보기
  9. Roberts Martin C. ; Tang Sanh D., Method for forming an integrated circuit interconnect using a dual poly process.
    상세보기
  10. Roberts, Martin C.; Tang, Sanh D., Method for forming an integrated circuit interconnect using a dual poly process.
    상세보기
  11. Roberts, Martin C.; Tang, Sanh D., Method for forming an integrated circuit interconnect using a dual poly process.
    상세보기
  12. Nogami Takeshi ; Lopatin Sergey ; Pramanick Shekhar, Method for making multilayered coaxial interconnect structure.
    상세보기
  13. Duesman, Kevin G.; Farnworth, Warren M., Method of forming semiconductor device utilizing die active surfaces for laterally extending die internal and external connections.
    상세보기
  14. Yu, Chen-Hua; Tseng, Horng-Huei, Method of selectively making copper using plating technology.
    상세보기
  15. Nogami Takeshi ; Lopatin Sergey ; Pramanick Shekhar, Multi-layered coaxial interconnect structure.
    상세보기
  16. Bernstein, Kerry; Bryant, Andres; Howell, Wayne J.; Klaasen, William A.; Pricer, Wilbur D.; Stamper, Anthony K., On chip alpha-particle detector.
    상세보기
  17. Hoshino,Yutaka; Ikeda,Shuji; Yoshida,Isao; Kamohara,Shiro; Kawakami,Megumi; Miyake,Tomoyuki; Morikawa,Masatoshi, Power mosfet having conductor plug structured contacts.
    상세보기
  18. Harada,Yusuke, Semiconductor device.
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  19. Harada,Yusuke, Semiconductor device.
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  20. Hoshino, Yutaka; Ikeda, Shuji; Yoshida, Isao; Kamohara, Shiro; Kawakami, Megumi; Miyake, Tomoyuki; Morikawa, Masatoshi, Semiconductor device and a method of manufacturing the same.
    상세보기
  21. Hoshino, Yutaka; Ikeda, Shuji; Yoshida, Isao; Kamohara, Shiro; Kawakami, Megumi; Miyake, Tomoyuki; Morikawa, Masatoshi, Semiconductor device and a method of manufacturing the same.
    상세보기
  22. Hiroyuki Ohta JP; Hideo Miura JP; Kazushige Sato JP; Takeshi Kimura JP; Hiroo Masuda JP, Semiconductor device and method of fabricating same.
    상세보기
  23. Ohta, Hiroyuki; Miura, Hideo; Sato, Kazushige; Kimura, Takeshi; Masuda, Hiyoo, Semiconductor device and method of fabricating same.
    상세보기
  24. Aoyama,Junichi, Semiconductor device and method of manufacturing the same.
    상세보기
  25. Sung-Bong Kim KR, Semiconductor device having a multi-level metallization and its fabricating method.
    상세보기
  26. Hoshino, Yutaka; Ikeda, Shuji; Yoshida, Isao; Kamohara, Shiro; Kawakami, Megumi; Miyake, Tomoyuki; Morikawa, Masatoshi, Semiconductor device having a plurality of misfets formed on a main surface of a semiconductor substrate.
    상세보기
  27. Harada, Yusuke, Semiconductor device having damascene interconnection structure that prevents void formation between interconnections.
    상세보기
  28. Harada, Yusuke, Semiconductor device having damascene interconnection structure that prevents void formation between interconnections.
    상세보기
  29. Yusuke Harada JP, Semiconductor device having damascene interconnection structure that prevents void formation between interconnections.
    상세보기
  30. Harada, Yusuke, Semiconductor device having damascene interconnection structure that prevents void formation between interconnections having transparent dielectric substrate.
    상세보기
  31. Mika Shiiki JP; Jun Osanai JP, Semiconductor device having thin film resistor and method of manufacturing the same.
    상세보기
  32. Hoshino, Yutaka; Ikeda, Shuji; Yoshida, Isao; Kamohara, Shiro; Kawakami, Megumi; Miyake, Tomoyuki; Morikawa, Masatoshi, Semiconductor device including a power MISFET.
    상세보기
  33. Hoshino, Yutaka; Ikeda, Shuji; Yoshida, Isao; Kamohara, Shiro; Kawakami, Megumi; Miyake, Tomoyuki; Morikawa, Masatoshi, Semiconductor device including a power MISFET and method of manufacturing the same.
    상세보기
  34. Lowrey, Tyler A., Semiconductor devices including buried digit lines that are laterally offset from corresponding active-device regions.
    상세보기
  35. Gardner Mark I. ; Kadosh Daniel ; Spikes ; Jr. Thomas E., Semiconductor fabrication employing a local interconnect.
    상세보기
  36. Ikemasu, Shinichiroh; Okawa, Narumi, Semiconductor memory device having electrical connection by side contact.
    상세보기
  37. Park, Byeongju; Iyer, Subramanian S.; Kothandaraman, Chandrasekharan, Three-terminal antifuse structure having integrated heating elements for a programmable circuit.
    상세보기
  38. Duesman, Kevin G.; Farnworth, Warren M., Utilization of die active surfaces for laterally extending die internal and external connections.
    상세보기
  39. Duesman, Kevin G.; Farnworth, Warren M., Utilization of die active surfaces for laterally extending die internal and external connections.
    상세보기
  40. Duesman Kevin G. ; Farnworth Warren M., Utilization of die repattern layers for die internal connections.
    상세보기
  41. Duesman Kevin G. ; Farnworth Warren M., Utilization of die repattern layers for die internal connections.
    상세보기

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