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Integrated circuit with edge connections and method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/34
출원번호 US-0463388 (1995-06-05)
발명자 / 주소
  • Gaul Stephen Joseph (Melbourne FL)
출원인 / 주소
  • Harris Corporation (Palm Bay FL 02)
인용정보 피인용 횟수 : 61  인용 특허 : 26

초록

A surface mountable integrated circuit is disclosed. Dies 1041 with edge connections 1080 are coupled to each other with the edge connection and to a printed circuit board 1070.

대표청구항

An integrated circuit die with edge connectors comprising: a die of semiconductor material with first and second surfaces, an integrated circuit formed in the first surface, said die having an edge region with one or more edge surfaces disposed transverse to the first and second surfaces of the die,

이 특허에 인용된 특허 (26)

  1. Johnson Alfred H. (Poughkeepsie NY), Apertured semi-conductor device mounted on a substrate.
  2. Malhi Satwinder S. (Garland TX) Bean Kenneth E. (Richardson TX), Baseboard for orthogonal chip mount.
  3. Anthony Thomas R. (Schenectady NY) Cline Harvey E. (Schenectady NY), Deep diode lead throughs.
  4. Bickford Harry R. (57 Sherwood Ave. Ossining NY 10562) Bregman Mark F. (63 Old Washington Rd. Ridgefield CT 06877) Moskowitz Paul A. (R.D. #1 ; Box 343 ; Hunterbrook Rd. Yorktown Heights NY 10598) Pa, Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and pr.
  5. Lorenze ; Jr. ; Robert V. ; White ; William Joseph, Double sided hybrid mosaic focal plane.
  6. Lorenze ; Jr. Robert V. (Westford MA) White William J. (Chelmsford MA), Double sided hybrid mosaic focal plane.
  7. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  8. Simmons Arturo (Garland TX), Focal plane array structure including a signal processing system.
  9. Kurosawa Keiji (Nagano JPX) Yamamoto Kenji (Nagano JPX) Yamashita Mitsuo (Nagano JPX) Mitsui Hisami (Nagano JPX) Miyabara Ayako (Nagano JPX) Miyagawa Kiyotaka (Suzaka JPX) Imura Takayoshi (Nagano JPX, Hollow multilayer printed wiring board.
  10. Eide Floyd K. (Huntington Beach CA), IC chip package having chip attached to and wire bonded within an overlying substrate.
  11. Soclof, Sidney I., Integrated circuit chip transmission line.
  12. Blocker ; III Truman G. (Richardson TX), Interconnection in multi element planar structures.
  13. Morris ; Raymond A. ; Viola ; Jr. ; Thomas J., Low parasitic capacitance and resistance beamlead semiconductor component and method of manufacture.
  14. Reid Lee R. (Plano TX), Method for fabricating a semiconductor contact and interconnect structure using orientation dependent etching and thermo.
  15. Benjamin James A. (Waukesha WI) Schutten Herman P. (Milwaukee WI) Lade Robert W. (Fort Myers FL), Multi-channel power JFET with buried field shaping regions.
  16. Okabe Kazuya (Furukawa JPX) Kasama Yasuhiko (Izumi JPX) Seki Hitoshi (Izumi JPX) Iwasaki Chisato (Furukawa JPX), Optical sensor including shortcircuit protection having notched electrode regions.
  17. Ng Kwok K. (Union NJ) Sze Simon M. (Berkeley Heights NJ), Packaging microminiature devices.
  18. Abbas Shakir A. (Wappingers Falls NY) Dockerty Robert C. (Highland NY) Poponiak Michael R. (Newburgh NY), Process for forming apertures in silicon bodies.
  19. Kurosawa Keiji (Nagano JPX) Yamamoto Kenji (Nagano JPX) Yamashita Mirsuo (Nagano JPX) Mitsui Hisami (Nagano JPX) Miyabara Ayako (Nagano JPX) Miyagawa Kiyotaka (Suzaka JPX) Imura Takayoshi (Nagano JPX, Process for manufacturing hollow multilayer printed wiring board.
  20. Martyniak Gerald J. (Indianapolis IN), Processes of making two-sided printed circuit boards, with through-hole connections.
  21. Clements Ken (Santa Cruz CA), Semiconductor wafer array.
  22. Clements Ken (Santa Cruz CA), Semiconductor wafer array with electrically conductive compliant material.
  23. Hanes Maurice H. (Murrysville) Clarke Rowland C. (Bell Township) Driver Michael C. (Elizabeth Township PA), Semiconductor wafer with circuits bonded to a substrate.
  24. Grinberg Jan (Los Angeles CA) Jacobson Alexander D. (Los Angeles CA) Chow Kuen (Thousand Oaks CA), Three-dimensionally structured microelectronic device.
  25. Herberg Helmut (Munich DEX), Thyristor with a multi-layer semiconductor body with a pnpn layer sequence and a method for its manufacture with a {111}.
  26. Angiulli John M. (Lagrangeville NY) Kolankowsky Eugene S. (Wappingers Falls NY) Konian Richard R. (Poughkeepsie NY) Wu Leon L. (Hopewell Junction NY), Vertical chip mount memory package with packaging substrate and memory chip pairs.

이 특허를 인용한 특허 (61)

  1. Farrar, Paul A., Angled edge connections for multichip structures.
  2. Farrar, Paul A., Angled edge connections for multichip structures.
  3. Farrar, Paul A., Angled edge connections for multichip structures.
  4. Moden, Walter L., Apparatus and method for packaging circuits.
  5. Walter L. Moden, Apparatus and method for packaging circuits.
  6. Farnworth, Warren M.; Corisis, David J.; Akram, Salman, Apparatus for forming modular sockets using flexible interconnects and resulting structures.
  7. Farnworth,Warren M.; Corisis,David J.; Akram,Salman, Apparatus for forming modular sockets using flexible interconnects and resulting structures.
  8. Farnworth,Warren M.; Corisis,David J.; Akram,Salman, Apparatus for forming modular sockets using flexible interconnects and resulting structures.
  9. Kinsman,Larry D., Back-to-back semiconductor device assemblies.
  10. Larry D. Kinsman, Back-to-back semiconductor device module, assemblies including the same and methods.
  11. Ference, Thomas G.; Howell, Wayne J.; Tonti, William R.; Williams, Richard Q., Chip edge interconnect apparatus and method.
  12. Ulmer, Kenneth R.; Cecere, John M., Circuit board having side attach pad traces through buried conductive material.
  13. Seidemann, Georg; Albers, Sven; Ossiander, Teodora; Skinner, Michael; Barth, Hans-Joachim; Gossner, Harald; Mahnkopf, Reinhard; Mueller, Christian; Molzer, Wolfgang, Die edge side connection.
  14. Ulmer Kenneth R., Embedded trimmable resistors.
  15. Fraley,Lawrence R.; Markovich,Voya R., Information handling system.
  16. Badehi, Avner, Integrated circuit device.
  17. Badehi, Avner, Integrated circuit device.
  18. Badehi, Avner, Integrated circuit device.
  19. Farnworth Warren M. ; Corisis David J. ; Akram Salman, Method and apparatus for forming modular sockets using flexible interconnects and resulting structures.
  20. Farnworth, Warren M.; Corisis, David J.; Akram, Salman, Method and apparatus for forming modular sockets using flexible interconnects and resulting structures.
  21. Farnworth,Warren M.; Corisis,David J.; Akram,Salman, Method and apparatus for forming modular sockets using flexible interconnects and resulting structures.
  22. Warren M. Farnworth ; David J. Corisis ; Salman Akram, Method and apparatus for forming modular sockets using flexible interconnects and resulting structures.
  23. Farnworth, Warren M.; Corisis, David J.; Akram, Salman, Method for forming modular sockets using flexible interconnects and resulting structures.
  24. Farnworth, Warren M.; Corisis, David J.; Akram, Salman, Method for forming modular sockets using flexible interconnects and resulting structures.
  25. Warren M. Farnworth ; David J. Corisis ; Salman Akram, Method for forming modular sockets using flexible interconnects and resulting structures.
  26. Ulmer Kenneth R. ; Cecere John M., Method for preparing side attach pad traces through buried conductive material.
  27. Ulmer, Kenneth R., Method of forming trimmable resistors.
  28. Fraley, Lawrence R.; Markovich, Voya, Method of making a multi-chip electronic package having laminate carrier.
  29. Kinsman,Larry D., Methods for securing vertically mountable semiconductor devices in back-to back relation.
  30. Yuan, Lei; Cho, Jin; Kye, Jongwook; Levinson, Harry J., Methods of forming contacts for semiconductor devices using a local interconnect processing scheme.
  31. Farnworth Warren M. ; Corisis David J. ; Akram Salman, Modular die sockets with flexible interconnects for packaging bare semiconductor die.
  32. Farnworth,Warren M.; Corisis,David J.; Akram,Salman, Modular sockets using flexible interconnects.
  33. Farnworth,Warren M.; Corisis,David J.; Akram,Salman, Modular sockets using flexible interconnects.
  34. Fraley,Lawrence R.; Markovich,Voya R., Multi-chip electronic package having laminate carrier and method of making same.
  35. Mauder,Anton, Semiconductor component and corresponding fabrication/mounting method.
  36. Robert E. Terrill, Semiconductor device and method of fabrication.
  37. Farnworth, Warren M.; Kinsman, Larry D.; Moden, Walter L., Semiconductor device including edge bond pads.
  38. Farnworth Warren M. ; Kinsman Larry D. ; Moden Walter L., Semiconductor device including edge bond pads and methods.
  39. Farnworth Warren M. ; Kinsman Larry D. ; Moden Walter L., Semiconductor device including edge bond pads and methods.
  40. Farnworth, Warren M.; Kinsman, Larry D.; Moden, Walter L., Semiconductor device including edge bond pads and methods.
  41. Warren M. Farnworth ; Larry D. Kinsman ; Walter L. Moden, Semiconductor device including edge bond pads and methods.
  42. Warren M. Farnworth ; Larry D. Kinsman ; Walter L. Moden, Semiconductor device including edge bond pads and methods.
  43. Farnworth, Warren M.; Kinsman, Larry D.; Moden, Walter L., Semiconductor device including edge bond pads and related methods.
  44. Kevin C. Gerlock ; Klaas B. Bol, Support and cooling architecture for RF printed circuit boards having multi-pin square post type connectors for RF connectivity.
  45. Pogge,H. Bernhard; Yu,Roy, Three-dimensional device fabrication method.
  46. Larry D. Kinsman ; Jerry M. Brooks ; Warren M. Farnworth ; Walter L. Moden ; Terry R. Lee, Vertical surface mount assembly.
  47. Kinsman Larry D. ; Brooks Jerry M. ; Farnworth Warren M. ; Moden Walter L. ; Lee Terry R., Vertical surface mount assembly and methods.
  48. Kinsman Larry D. ; Brooks Jerry M. ; Farnworth Warren M. ; Moden Walter L. ; Lee Terry R., Vertical surface mount assembly and methods.
  49. Kinsman Larry D. ; Brooks Jerry M. ; Farnworth Warren M. ; Moden Walter L. ; Lee Terry R., Vertical surface mount assembly and methods.
  50. Kinsman, Larry D.; Brooks, Jerry M.; Farnworth, Warren M.; Moden, Walter L.; Lee, Terry R., Vertical surface mount assembly and methods.
  51. Kinsman, Larry D.; Brooks, Jerry M.; Farnworth, Warren M.; Moden, Walter L.; Lee, Terry R., Vertical surface mount assembly and methods.
  52. Kinsman,Larry D.; Brooks,Jerry M.; Farnworth,Warren M.; Moden,Walter L.; Lee,Terry R., Vertical surface mount assembly and methods.
  53. Larry D. Kinsman ; Jerry M. Brooks ; Warren M. Farnworth ; Walter L. Moden ; Terry R. Lee, Vertical surface mount assembly and methods.
  54. Kinsman Larry D., Vertical surface mount package utilizing a back-to-back semiconductor device module.
  55. Kinsman, Larry D., Vertical surface mount package utilizing a back-to-back semiconductor device module.
  56. Kinsman, Larry D., Vertical surface mount package utilizing a back-to-back semiconductor device module.
  57. Larry D. Kinsman, Vertical surface mount package utilizing a back-to-back semiconductor device module.
  58. Kinsman Larry D., Vertically mountable semiconductor device and methods.
  59. Kinsman Larry D., Vertically mountable semiconductor device and methods.
  60. Kinsman, Larry D., Vertically mountable semiconductor device and methods.
  61. Larry D. Kinsman, Vertically mountable semiconductor device and methods.
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