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In a synchronizing circuit receiving a bit stream including a synchronous pattern and various kinds of information bits, for outputting a synchronous signal, there is provided a synchronous pattern register which is previously set with known information bits of the layer, the bit rate and the sampli

In a synchronizing circuit receiving a bit stream including a synchronous pattern and various kinds of information bits, for outputting a synchronous signal, there is provided a synchronous pattern register which is previously set with known information bits of the layer, the bit rate and the sampling frequency. A synchronous pattern detecting circuit is configured not to recognize as a synchronous pattern, a synchronous pattern having the values other than previously set values. With this arrangement, it is possible to remarkably reduce probability that a quasi synchronous pattern is detected as the synchronous pattern, and therefore, it is possible to minimize missing of sound corresponding to the digital audio signal.

대표청구항 ▼

A synchronizing circuit configured to receive a bit stream including header information having a synchronous pattern and frame length determining information in each frame, and to detect a frame boundary so as to generate a frame synchronous signal corresponding to the header information, the synchr

A synchronizing circuit configured to receive a bit stream including header information having a synchronous pattern and frame length determining information in each frame, and to detect a frame boundary so as to generate a frame synchronous signal corresponding to the header information, the synchronizing circuit comprising: a synchronous pattern holding means for holding an expected pattern value corresponding to at least a portion of said frame length determining a data converting means for converting said bit stream of said synchronous pattern and said frame length determining information into parallel data; a synchronous pattern detecting means for detecting said synchronous pattern and said frame length determining information from said parallel data, and generating a synchronous pattern detection signal when said synchronous pattern and said frame length determining information from said parallel data are consistent with a predetermined pattern and when a portion of said frame length determining information from said parallel data is consistent with said expected pattern value; and a synchronous pattern discriminating means receiving said synchronous pattern detection signal, for generating a predetermined synchronous signal.